公开(公告)号：US20130058172A1

公开(公告)日：2013-03-07

申请号：US13224562

申请日：2011-09-02

Applicant: Hari M. Rao ,  Esin Terzioglu ,  Sei Seung Yoon

Inventor： Hari M. Rao ,  Esin Terzioglu ,  Sei Seung Yoon

IPC: G11C7/10

CPC classification number: G11C16/28 ,  G11C11/41 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/1204

Abstract: A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.

Abstract translation: 电路包括响应于存储测试代码的多个锁存器的多个电容器。 第一位线耦合到位单元并耦合到读出放大器。 第二位线耦合到位单元并耦合到读出放大器。 来自一组多个电容器的差分电荷被施加到第一位线和第二位线。 基于测试代码确定多个电容器的集合，并且测试代码独立于读出放大器的输出。

公开(公告)号：US08373785B2

公开(公告)日：2013-02-12

申请号：US13295895

申请日：2011-11-14

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: H04N3/14 ,  H04N5/335 ,  H01L31/062 ,  H01L31/113 ,  H01L27/00

CPC classification number: H04N5/361 ,  H04N5/235 ,  H04N5/243

Abstract: The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.

Abstract translation: 本发明包括用于有源像素传感器的运算放大器，其检测光能并产生与光能成比例的模拟输出。 有源像素传感器以多种不同的模式工作，包括：信号积分模式，复位积分模式，列复位模式和列信号读出模式。 每种模式都会使运算放大器看到不同的输出负载。 因此，运算放大器包括可变反馈电路，以提供为有源像素传感器的每个操作模式提供足够的放大器稳定性的补偿。 例如，运算放大器包括一组反馈电容器，其中的一个或多个基于操作模式选择，以提供足够的相位裕度用于稳定性，而且还考虑了操作模式的增益和带宽要求。

公开(公告)号：US08004912B2

公开(公告)日：2011-08-23

申请号：US12491864

申请日：2009-06-25

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C29/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括适于被移出使用的至少一个有源预解码器; 以及至少一个适于被移入使用的冗余预解码器。

公开(公告)号：US07852688B2

公开(公告)日：2010-12-14

申请号：US12108282

申请日：2008-04-23

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C7/22

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator.

Abstract translation: 在一个实施例中，存储器包括：根据字线和列布置的每个列对应于位线的存储器单元的阵列; 读出放大器，其适于耦合到位线以感测来自存储器单元阵列的所选择的单元的二进制内容，所述读出放大器响应于感测命令感测所述二进制内容; x解码器被配置为响应于由时钟边缘触发的地址的解码来断言所选择的一个字线，其中所选择的字线的断言对相应的存取晶体管开关以在位线上产生电压; 以及位线复制电路，其适于复制位线的显影，所述位线复制电路包括耦合在副本位线和复制存储器单元之间的复制存取晶体管，其中复制存取晶体管响应于时钟沿被接通 使得复制存储器单元将副本位线拉到地，位线复制电路还包括响应于将复制位线的电压与阈值进行比较而断言输出的比较器，感测命令是缓冲版本 比较器的输出。

公开(公告)号：US07852113B2

公开(公告)日：2010-12-14

申请号：US12326086

申请日：2008-12-01

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/0016

Abstract: In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.

Abstract translation: 在一个实施例中，提供了一种泄漏减小电路，其包括：虚拟电源节点; 耦合在虚拟电源节点和电源节点之间的第一PMOS晶体管; 第二PMOS晶体管，其具有耦合到所述电源节点的源极; 以及耦合在所述第二PMOS晶体管的漏极和所述虚拟电源节点之间的天然NMOS晶体管，所述天然NMOS晶体管具有由所述电源节点驱动的栅极。

公开(公告)号：US07738308B2

公开(公告)日：2010-06-15

申请号：US12016738

申请日：2008-01-18

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

IPC: G11C7/00

CPC classification number: G11C29/789

Abstract: In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.

Abstract translation: 在一个实施例中，存储器包括使用二进制单元来指示给定行或列的存储器单元是否有故障的行和/或列冗余体系结构。 二进制单元适于存储响应于对相应行或列的常规访问以及设置信号的断言的“修复真实”信号。

公开(公告)号：US07710811B2

公开(公告)日：2010-05-04

申请号：US12016602

申请日：2008-01-18

Applicant: Esin Terzioglu ,  Gil L Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil L Winograd ,  Morteza Cyrus Afghahi

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.

Abstract translation: 在一个实施例中，提供了一种存储器，其包括：以列形式布置的多个存储器单元，每列耦合到对应的位线; 感测放大器，其适于感测一对位线上的电压，以确定耦合到所述对中的所述位线中的第一位的所访问的存储器单元的二进制状态; 以及第一微调电容器，其具有直接耦合到所述一对位线之一的第一端子，所述第一微调电容器具有耦合到第一微调电容器信号的相对的第二端子，所述存储器适于改变所述第一微调电压 电容器信号，而感测放大器感测电压以确定所访问的存储器单元的二进制状态。

公开(公告)号：US07710755B2

公开(公告)日：2010-05-04

申请号：US12018996

申请日：2008-01-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C5/06

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column.

Abstract translation: 在一个实施例中，提供了动态随机存取存储器（DRAM），其包括：布置成行和列的多个存储单元，其中每个存储单元包括耦合到存储晶体管的存取晶体管，每个存取晶体管布置成矩形 具有长度大于宽度的长度，长度与相应的列对齐，所述存取晶体管耦合到具有大于矩形形状的宽度的宽度的存储晶体管，所述存取晶体管的长度与对应的行对齐， 每个存储单元是L形的，并且其中每列中的L形存储单元相对于相邻列交错排列，使得给定列中的L形存储单元与L形存储单元互锁 相邻列。

公开(公告)号：US07598480B2

公开(公告)日：2009-10-06

申请号：US11606118

申请日：2006-11-30

Applicant: Esin Terzioglu ,  Mehdi Hatamian ,  Ali Anvar

Inventor： Esin Terzioglu ,  Mehdi Hatamian ,  Ali Anvar

IPC: H03G3/20 ,  G06K9/38

CPC classification number: H04N5/235 ,  H04N5/243 ,  H04N5/361 ,  H04N5/3658 ,  H04N5/378

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract translation: 成像装置包括多个光电二极管，其作为在单个CMOS衬底上排列成多列的光学像素。 检查多个像素传感器或光电二极管的输出以确定一个像素或像素区域是否处于饱和状态。 如果是这样，则调整像素增益以校正或补偿该区域中的图像失真。 例如，可以调整充电放大器或运算放大器的增益以校正饱和。 这可以实时完成，因为硬件正在调整而不是软件。

公开(公告)号：US20090230990A1

公开(公告)日：2009-09-17

申请号：US12464629

申请日：2009-05-12

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件元件的可编程保险丝与多个存储器单元一起被使用以指示至少一个存储器单元不可用并且应该被移出而不工作。 软件可编程元件包括可编程寄存器，其适于移位指示至少一个存储器单元有缺陷的适当值。 硬件元件包括一个带可编程寄存器的保险丝。 移位由软件可编程保险丝或硬保险丝指示。 软熔丝寄存器可以链接在一起形成移位寄存器。