中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

317 records (took 0.031 seconds)

    RF circuit with stacked printed circuit boards
    92.
    发明授权
    RF circuit with stacked printed circuit boards 有权
    RF电路与堆叠的印刷电路板

    公开(公告)号：US07725095B2

    公开(公告)日：2010-05-25

    申请号：US10586292

    申请日：2004-11-04

    Applicant: Tiam Fatt Tey ,  Lye Yoong Lum ,  Feng Lin

    Inventor： Tiam Fatt Tey ,  Lye Yoong Lum ,  Feng Lin

    IPC: H04B1/08 ,  H04N5/30

    CPC classification number: H05K7/1417 ,  H05K1/144 ,  H05K9/002

    Abstract: An RF unit comprises a tuner, a demodulator and a mixer. At least the tuner and the mixer are disposed on separate first and second substrates. The RF unit further comprises a housing accommodating the first and second substrates. The first substrate and the second substrate are arranged on different levels inside the housing and maintain a predetermined distance between each other.

    Abstract translation: RF单元包括调谐器，解调器和混频器。 至少调谐器和混合器设置在分开的第一和第二基板上。 RF单元还包括容纳第一和第二基板的壳体。 第一基板和第二基板布置在壳体内的不同水平面上并保持彼此之间的预定距离。

    System and Method to Improve the Efficiency of Synchronous Mirror Delays and Delay Locked Loops
    93.
    发明申请
    System and Method to Improve the Efficiency of Synchronous Mirror Delays and Delay Locked Loops 失效
    提高同步镜延迟和延迟锁定环的效率的系统和方法

    公开(公告)号：US20100026351A1

    公开(公告)日：2010-02-04

    申请号：US12574847

    申请日：2009-10-07

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: H03L7/00

    CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/0814

    Abstract: A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions. The invention increases the efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range.

    Abstract translation: 公开了一种用于同步镜延迟或延迟锁定环路的相位检测系统，以便减少所需的延迟级数，从而提高效率。 本发明包括采用每个具有定时特性的时钟输入信号和时钟延迟或反馈信号，并且基于信号的定时特性来区分四个条件。 相位检测器和相关电路然后基于信号的定时特性来确定信号处于多个相位条件中的哪一个。选择器通过定时选择要被引入同步镜延迟或延迟锁定环路的信号 相位条件的特征。 该系统能够利用时钟输入信号的下降时钟边沿，并且在特定相位条件下锁定时间减少。 本发明通过在保持工作范围的同时减少SMD或DLL中的有效延迟级来提高电路的效率。

    Phase detector for reducing noise
    94.
    发明授权
    Phase detector for reducing noise 失效
    相位检测器，用于降低噪音

    公开(公告)号：US07639090B2

    公开(公告)日：2009-12-29

    申请号：US12324077

    申请日：2008-11-26

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/089

    Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

    Abstract translation: 本发明提供一种降低噪声的方法和装置。 该装置包括相位检测器，其适于确定第一和第二信号之间的相位差，适于基于所确定的相位差产生控制信号的第一电路和第二电路。 第二电路适于接收第三信号，接收第四信号，基于控制信号修改第四信号，并将第三信号和修改的第四信号提供给相位检测器作为第一和第二信号。

    Delay-lock loop and method adapting itself to operate over a wide frequency range
    95.
    发明授权
    Delay-lock loop and method adapting itself to operate over a wide frequency range 有权
    延迟锁定环路和方法适应于在宽频率范围内工作

    公开(公告)号：US07619458B2

    公开(公告)日：2009-11-17

    申请号：US11521837

    申请日：2006-09-14

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: H03K3/00

    CPC classification number: G11C29/02 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0409

    Abstract: A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.

    Abstract translation: 延迟锁定环路接收来自接收参考时钟信号的可编程分频器的输出端的输入时钟信号。 延迟锁定环包括产生具有不同相位的多个延迟时钟信号的电压控制延迟线。 多个延迟的时钟信号被组合以产生多个输出信号。 在初始化期间，初始化电路将延迟线的延迟设定为最小延迟值，然后将该延迟值与输入时钟信号的周期进行比较。 基于该比较，初始化电路对可编程分频器进行编程，并调整组合的延迟时钟信号的数量以产生输出信号。 更具体地，随着参考时钟信号的频率增加，分频器被编程为除以更大的数量，并且更大数量的延迟时钟信号被组合以产生输出信号。

    CLOCK DISTRIBUTION APPARATUS, SYSTEMS, AND METHODS
    97.
    发明申请
    CLOCK DISTRIBUTION APPARATUS, SYSTEMS, AND METHODS 有权
    时钟分配设备，系统和方法

    公开(公告)号：US20090240970A1

    公开(公告)日：2009-09-24

    申请号：US12051745

    申请日：2008-03-19

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: G06F1/04

    CPC classification number: G06F1/10 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

    Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 公开了用于至少部分地基于集成电路的操作条件来调整由时钟分配网络接收的功率的装置，系统和方法。 公开了附加装置，系统和方法。

    Phase detector for reducing noise
    98.
    发明授权
    Phase detector for reducing noise 有权
    相位检测器，用于降低噪音

    公开(公告)号：US07463099B2

    公开(公告)日：2008-12-09

    申请号：US11524842

    申请日：2006-09-21

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: H03D3/00

    CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/089

    Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

    Abstract translation: 本发明提供一种降低噪声的方法和装置。 该装置包括相位检测器，其适于确定第一和第二信号之间的相位差，适于基于所确定的相位差产生控制信号的第一电路和第二电路。 第二电路适于接收第三信号，接收第四信号，基于控制信号修改第四信号，并将第三信号和修改的第四信号提供给相位检测器作为第一和第二信号。

    Bias generator with feedback control
    99.
    发明授权
    Bias generator with feedback control 有权
    带反馈控制的偏置发生器

    公开(公告)号：US07449939B2

    公开(公告)日：2008-11-11

    申请号：US11895419

    申请日：2007-08-24

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: G05F1/10

    CPC classification number: H03L7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

    Abstract: A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal. The voltage of the control signal is varied from the initial voltage until an output clock signal from the voltage controlled delay line is detected by the bias generator.

    Abstract translation: 一种偏置发生器，用于通过向电压控制的延迟线提供具有初始电压的控制信号并监视输出时钟信号的可变延迟线来初始化电压控制延迟线。 控制信号的电压从初始电压变化，直到来自电压控制的延迟线的输出时钟信号被偏置发生器检测到。

    Loop filtering for fast PLL locking
    100.
    发明授权
    Loop filtering for fast PLL locking 有权
    循环滤波用于快速PLL锁定

    公开(公告)号：US07443761B2

    公开(公告)日：2008-10-28

    申请号：US11358266

    申请日：2006-02-21

    Applicant: Feng Lin

    Inventor： Feng Lin

    IPC: G11C8/00

    CPC classification number: H03L7/081 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1075

    Abstract: Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage of the DLL path to a loop filter of the DLL path. The method includes locking a DLL voltage while applying the control voltage of the DLL path to the loop filter of the DLL path. The method also includes transferring the control voltage from the loop filter of the DLL path to a loop filter of the PLL path after the DLL voltage locks.

    Abstract translation: 提供了锁相环（PLL）锁定的方法，电路，器件和系统。 锁定PLL的方法包括锁定延迟锁定环（DLL）路径，同时将DLL路径的控制电压施加到DLL路径的环路滤波器。 该方法包括锁定DLL电压，同时将DLL路径的控制电压施加到DLL路径的环路滤波器。 该方法还包括在DLL电压锁定之后将控制电压从DLL路径的环路滤波器传送到PLL路径的环路滤波器。

Patent Agency Ranking