公开(公告)号：US4922134A

公开(公告)日：1990-05-01

申请号：US309386

申请日：1989-02-10

申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans-Dieter Oberle

发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans-Dieter Oberle

IPC分类号： G11C29/00 ,  G11C29/04

CPC分类号： G11C29/785

摘要： A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.

摘要翻译： 一种集成半导体存储器的冗余解码器，其具有包含开关晶体管的多个解码器级和具有可分离连接断开和完整的各自条件的可分离连接，以及至少一个充电晶体管，包括： 解码器级，连接到开关晶体管和各个解码器级的可分离连接之间的寻址电路，当相应的可分离连接处于其完整状态时，寻址电路可电可模拟。

公开(公告)号：US4498154A

公开(公告)日：1985-02-05

申请号：US340781

申请日：1982-01-19

申请人： Kurt Hoffmann

发明人： Kurt Hoffmann

IPC分类号： G11C11/419 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  H01L29/78 ,  G11C11/24

CPC分类号： G11C11/4097

摘要： Monolithically integrated semiconductor memory with a matrix of identical storage cells arranged rows and columns in the form of a coordinated MOS field-effect transistors and storage capacitors in the form of an MOS capacitor and wherein, also, a comparator and a comparison cell is formed of one of the storage cells are associated with each matrix column, including a method for bridging over a point of interruption in a course of a bit line extending from one to another of at least two adjacent storage cells of at least one column. The bridging method may be an MOS field-effect transistor having a current-carrying path over which the point of interruption is bridged.

摘要翻译： 具有相同存储单元的矩阵的单片集成半导体存储器以MOS协调MOS场效应晶体管和存储电容器的形式布置行和列，其形式为MOS电容器，并且比较单元和比较单元也由 存储单元之一与每个矩阵列相关联，包括用于跨越至少一列的至少两个相邻存储单元中的一个位线延伸的位线的过程中的中断点的桥接的方法。 桥接方法可以是具有通过中断点桥接的载流路径的MOS场效应晶体管。

公开(公告)号：US4271461A

公开(公告)日：1981-06-02

申请号：US36070

申请日：1979-05-04

申请人： Kurt Hoffmann ,  Karl Zapf

发明人： Kurt Hoffmann ,  Karl Zapf

IPC分类号： G11C11/407 ,  H02M3/07 ,  H02P13/22

CPC分类号： H02M3/07

摘要： A clock-controlled dc converter is provided in integrated semiconductor MOS technology and serves the supply voltage of integrated MOS circuits, particularly dynamic memories. The converter comprises a clock pulse generator having two outputs, supplying sequences of clock pulses which are inverted with respect to one another, which pulses are connected to the two clock pulse inputs of a first pulse level shifter. The first pulse level shifter comprises a bistable flip-flop lying at a supply potential, and which is switched as a level shifter. The two outputs of the first level shifter are connected, on the one hand, to the output of a voltage converter by way of the source-drain circuit of a respective field effect transistor. On the other hand, the two outputs are connected to the supply input of a respective pulse voltage doubler, which are in turn directly charged by a respective output of the clock pulse generator. The two pulse voltage doublers supply the clock pulse supply for a second pulse level shifter, likewise constructed as a bistable flip-flop, by way of the two outputs of which the connection between the outputs of the first level shifter and the output of the voltage comparator is controlled. The doubled supply voltage appears at the output of the voltage converter.

摘要翻译： 集成半导体MOS技术提供时钟控制的直流转换器，并为集成的MOS电路，特别是动态存储器提供电源电压。 该转换器包括具有两个输出的时钟脉冲发生器，提供相对于彼此反相的时钟脉冲序列，哪些脉冲连接到第一脉冲电平移位器的两个时钟脉冲输入。 第一脉冲电平移位器包括位于电源电位的双稳态触发器，并被切换为电平移位器。 一方面，第一电平移位器的两个输出端通过各自的场效应晶体管的源极 - 漏极电路连接到电压转换器的输出端。 另一方面，两个输出端连接到相应的脉冲倍压器的电源输入端，这些脉冲倍压器又由时钟脉冲发生器的相应输出端直接充电。 两个脉冲电压倍增器为同样构造为双稳态触发器的第二脉冲电平移位器提供时钟脉冲电源，通过其两个输出，第一电平移位器的输出与电压的输出之间的连接 比较器被控制。 在电压转换器的输出端出现双倍的电源电压。

公开(公告)号：US4206471A

公开(公告)日：1980-06-03

申请号：US943065

申请日：1978-09-18

申请人： Kurt Hoffmann ,  Reiner Sigusch

发明人： Kurt Hoffmann ,  Reiner Sigusch

IPC分类号： H01L27/10 ,  G11C11/35 ,  G11C11/403 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/35 ,  G11C11/403 ,  Y10S257/92

摘要： A semiconductor storage element is disclosed having a storage capacitor whose storage electrode is arranged above a doped semiconductor layer. The storage electrode is formed of a portion of a strip-like reference potential line which is separated from the semiconductor layer by a thin insulating layer. A transfer gate is also provided adjacent to the storage electrode which is formed from a portion of a strip-like word line likewise separated from the semiconductor layer by a thinner insulating layer. An oppositely doped zone is arranged at a surface of the semiconductor layer and serves as a bit line. The word line and the reference potential line run parallel to one another and are arranged directly adjacent to one another. When a potential is connected to the transfer gate, the bit line doped zone may be selectively conductively connected to the storage zone. The reference potential line for one group of the storage elements can be also used as a word line for another group of the storage elements.

摘要翻译： 公开了一种半导体存储元件，其具有存储电容器，其存储电极布置在掺杂半导体层的上方。 存储电极由薄膜绝缘层与半导体层分离的带状基准电位线的一部分形成。 传输门也邻近存储电极设置，该存储电极由类似于半导体层的绝缘层较薄的条状字线的一部分形成。 在该半导体层的表面上配置相对掺杂区，作为位线。 字线和参考电位线彼此平行延伸并且彼此直接布置。 当电位连接到传输门时，位线掺杂区可以选择性地导电地连接到存储区。 一组存储元件的参考电位线也可以用作另一组存储元件的字线。

公开(公告)号：US4156289A

公开(公告)日：1979-05-22

申请号：US872443

申请日：1978-01-26

申请人： Kurt Hoffmann ,  Rudolf Mitterer

发明人： Kurt Hoffmann ,  Rudolf Mitterer

IPC分类号： H01L27/10 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L29/7827 ,  G11C11/404 ,  H01L27/10823 ,  H01L29/4236

摘要： A semiconductor memory has at least one V-MOS transistor which includes a trench and a storage capacitor. A semiconductor substrate is doped with concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second conductivity type opposite to the first conductivity type. At least two additional layers are divided by the trench and have alternately differing conductivity types, the two additional layers and the buried layer being produced by diffusion and/or implantation.

摘要翻译： 半导体存储器具有包括沟槽和存储电容器的至少一个V-MOS晶体管。 半导体衬底掺杂有第一导电类型的浓度中心，并且具有掺杂有与第一导电类型相反的第二导电类型的浓度中心的掩埋层。 至少两个附加层被沟槽划分并且具有交替不同的导电类型，两个附加层和掩埋层通过扩散和/或植入而产生。

公开(公告)号：US4134033A

公开(公告)日：1979-01-09

申请号：US814998

申请日：1977-07-12

申请人： Kurt Hoffmann ,  Manfred Mauthe

发明人： Kurt Hoffmann ,  Manfred Mauthe

IPC分类号： G11C27/04 ,  A01D46/28 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  H01L29/768 ,  H03K5/02 ,  H03K5/18 ,  G11C7/00 ,  H03K17/04

CPC分类号： H03K5/023 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  G11C19/285 ,  H01L29/76825

摘要： A method and apparatus is disclosed for a fast switching digital differential amplifier system useful in regenerating information signals in charge coupled devices. The amplifier system has a first capacitance at an input point which is charged and discharged in accordance with a binary "0" or binary "1" at the input. A second capacitance and an output capacitance is provided with a predetermined charge thereon. In the event of a binary "1", the predetermined charge on the second and output capacitance is retained while the first capacitance is discharged. In the event of a binary "0", the second and output capacitances are discharged via a current sink. A flip-flop is connected to the output capacitance for accelerating the discharge of the same. Switching transistors are additionally provided for activating the flip-flop to achieve the desired fast-switching.

摘要翻译： 公开了一种用于在电荷耦合器件中再生信息信号的快速开关数字差分放大器系统的方法和装置。 放大器系统在输入点处具有根据输入端的二进制“0”或二进制“1”进行充放电的第一电容。 在其上提供预定电荷的第二电容和输出电容。 在二进制“1”的情况下，在第一电容放电的同时保持第二和输出电容上的预定电荷。 在二进制“0”的情况下，第二和输出电容通过电流接收器放电。 触发器连接到输出电容以加速其放电。 另外提供开关晶体管用于激活触发器以实现期望的快速切换。

公开(公告)号：US4121117A

公开(公告)日：1978-10-17

申请号：US720050

申请日：1976-09-02

申请人： Kurt Hoffmann ,  Gottfried Wotruba

发明人： Kurt Hoffmann ,  Gottfried Wotruba

IPC分类号： G11C27/04 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  H01L29/768 ,  H03K5/02 ,  H01L27/10 ,  H01L29/78

CPC分类号： H03K5/023 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  G11C19/285 ,  H01L29/76825

摘要： Regenerating amplifier for use with two charge coupled devices comprising field effect transistors to pre-charge the output diffusion capacitance of an output charge coupled device and the input diffusion capacitance of an input charge coupled device. The output diffusion capacitance is discharged by the arrival of output charge, in turn holding off an input gate such that the charge on the input diffusion capacitance is not shifted into the input charge coupled device. Various embodiments having control potentials and a field effect transistor to fully discharge the input diffusion capacitance of an input charge coupled device being usable with a plurality of input charge coupled devices having corresponding output charge coupled devices wherein individual charging transistors are available to charge each output diffusion zone capacitance with a common transistor being used to charge all input diffusion capacitances.

摘要翻译： 再生放大器用于包括场效应晶体管的两个电荷耦合器件，用于对输出电荷耦合器件的输出扩散电容和输入电荷耦合器件的输入扩散电容进行预充电。 输出扩散电容通过输出电荷的到达而放电，从而阻止输入栅极，使得输入扩散电容上​​的电荷不会移入输入电荷耦合器件。 具有控制电位的各种实施例和场效应晶体管完全放电输入电荷耦合器件的输入扩散电容，可与具有相应输出电荷耦合器件的多个输入电荷耦合器件一起使用，其中各个充电晶体管可用于对每个输出扩散进行充电 带有公共晶体管的区域电容用于对所有输入扩散电容充电。

公开(公告)号：US3997881A

公开(公告)日：1976-12-14

申请号：US612554

申请日：1975-09-11

申请人： Kurt Hoffmann

发明人： Kurt Hoffmann

IPC分类号： G11C11/41 ,  G11C11/412 ,  H03K3/356 ,  G11C11/40

CPC分类号： G11C11/412 ,  H03K3/356104

摘要： A static storage element circuit has two pairs of complementary-channel-field effect transistors. A word line and a bit line connect with at least one of the field effect transistors. Connection lines between the field effect transistors create parasitic capacitors for storing charges which control the logic state of the circuit.

摘要翻译： 静态存储元件电路具有两对互补沟道场效应晶体管。 字线和位线与至少一个场效应晶体管连接。 场效应晶体管之间的连接线产生用于存储控制电路的逻辑状态的电荷的寄生电容器。