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    METALLIC INTERCONNECT STRUCTURES WITH WRAP AROUND CAPPING LAYERS
    91.
    发明申请
    METALLIC INTERCONNECT STRUCTURES WITH WRAP AROUND CAPPING LAYERS 审中-公开

    公开(公告)号：US20200152510A1

    公开(公告)日：2020-05-14

    申请号：US16743115

    申请日：2020-01-15

    Applicant: International Business Machines Corporation

    Inventor： Cornelius Brown Peethala ,  Kedari Matam ,  Chih-Chao Yang ,  Theo Standaert

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

    Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

    Graded interconnect cap
    92.
    发明授权
    Graded interconnect cap 有权

    公开(公告)号：US10651083B2

    公开(公告)日：2020-05-12

    申请号：US15911313

    申请日：2018-03-05

    Applicant: International Business Machines Corporation

    Inventor： Andrew Tae Kim ,  Baozhen Li ,  Ernest Y. Wu ,  Chih-Chao Yang

    IPC: H01L23/52 ,  H01L21/768 ,  H01L23/532

    Abstract: A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.

    SILICON CARBIDE AND SILICON NITRIDE INTERCONNECTS
    93.
    发明申请
    SILICON CARBIDE AND SILICON NITRIDE INTERCONNECTS 审中-公开

    公开(公告)号：US20200144195A1

    公开(公告)日：2020-05-07

    申请号：US16178570

    申请日：2018-11-01

    Applicant: International Business Machines Corporation

    Inventor： Chih-Chao Yang

    IPC: H01L23/532 ,  H01L21/768

    Abstract: A method for fabricating an interconnect for integrated circuit is described. A recess is provided in a first dielectric layer comprising a first dielectric and a second dielectric layer comprised of a second dielectric. The first and second dielectric layers are disposed over a substrate. The second dielectric layer is disposed over the first dielectric layer. The recess is filled with a metal conductor. A chemical mechanical polishing process removes the metal conductor from field areas on the second dielectric layer. The second dielectric layer is removed. An interconnect element is created having a top face which protrudes higher than a top face of the first dielectric layer. The metal conductor of the interconnect element has direct contact with the first dielectric layer. In other aspects of the invention, the interconnect structure is described.

    PROTUBERANT CONTACTS FOR RESISTIVE SWITCHING DEVICES
    94.
    发明申请
    PROTUBERANT CONTACTS FOR RESISTIVE SWITCHING DEVICES 审中-公开

    公开(公告)号：US20200091427A1

    公开(公告)日：2020-03-19

    申请号：US16688500

    申请日：2019-11-19

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  Chih-Chao Yang ,  Lawrence A. Clevenger

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Embodiments of the invention provide a method of forming a crossbar array. The method includes forming conductive row electrode lines and forming conductive column electrode lines. The conductive column electrode lines form a plurality of crosspoints at intersections between the conductive row electrode lines and the conductive column electrode lines. An RSD is formed at each of the plurality of crosspoints, wherein the RSD includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact communicatively couples the first terminal through a first barrier liner to a first one of the conductive row electrode lines. The protuberant contact can be positioned with respect to the first barrier liner such that the first barrier liner does not impact the switchable conduction state of the active region.

    Modulating metal interconnect surface topography
    97.
    发明授权
    Modulating metal interconnect surface topography 有权

    公开(公告)号：US10522398B2

    公开(公告)日：2019-12-31

    申请号：US15692192

    申请日：2017-08-31

    Applicant: International Business Machines Corporation

    Inventor： Conal Murray ,  Chih-Chao Yang

    IPC: H01L21/768 ,  H01L21/321 ,  B24B37/04 ,  C09G1/02 ,  H01L23/532 ,  H01L21/311

    Abstract: A metal interconnect structure can be fabricated within an integrated circuit (IC). A recess can be created in an IC dielectric layer and a surface modulation liner can be formed by depositing two different metallic elements onto the surfaces of the recess. One metallic element can have a standard electrode potential greater than a standard electrode potential of an interconnect metal, and the other metallic element can have a standard electrode potential less than the standard electrode potential of the interconnect metal. A metal interconnect structure can be formed by filling the remainder of the recess with interconnect metal, which is physically separated from the dielectric layer by the surface modulation liner. The surface topography of the metal interconnect structure can be modulated with a polishing process, by removing a top portion of the interconnect metal and a top portion of the surface modulation liner.

    MIM CAPACITOR FOR IMPROVED PROCESS DEFECT TOLERANCE
    100.
    发明申请
    MIM CAPACITOR FOR IMPROVED PROCESS DEFECT TOLERANCE 审中-公开

    公开(公告)号：US20190341347A1

    公开(公告)日：2019-11-07

    申请号：US15970601

    申请日：2018-05-03

    Applicant: International Business Machines Corporation

    Inventor： Baozhen Li ,  Chih-Chao Yang ,  Andrew Tae Kim

    IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L23/525 ,  H01L21/768

    Abstract: A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.

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