公开(公告)号：US08901655B2

公开(公告)日：2014-12-02

申请号：US13969820

申请日：2013-08-19

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L27/13 ,  H01L29/86 ,  B82Y99/00

CPC classification number: H01L29/66545 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/888 ,  Y10S977/938

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中图案化至少一个第一/第二组纳米线和焊盘。 围绕用作晶体管器件的沟道区的第一组纳米线的每一个的一部分选择性地形成共形栅介质层。 第一金属栅极堆叠形成在共形栅极介电层上，围绕作为晶体管器件的沟道区域的第一组纳米线的每一个的栅极全部构型。 形成第二金属栅极叠层，围绕作为二极管器件的栅极全部配置的沟道区的第二组纳米线的每一个的一部分。

公开(公告)号：US08900934B2

公开(公告)日：2014-12-02

申请号：US13865519

申请日：2013-04-18

Applicant: International Business Machines Corporation

Inventor： Thomas N. Adam ,  Veeraraghavan S. Basker ,  Jinghong Li ,  Chung-Hsun Lin ,  Sebastian Naczas ,  Alexander Reznicek ,  Tenko Yamashita

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.

公开(公告)号：US20140332890A1

公开(公告)日：2014-11-13

申请号：US14023868

申请日：2013-09-11

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

Abstract translation: 在绝缘体层上形成至少一个半导体鳍片。 绝缘体层的一部分从至少一个半导体鳍片的下方蚀刻。 选择绝缘体的蚀刻部分的量使得金属栅极电极层填充绝缘体层的凹陷表面和至少一个半导体鳍片的底表面之间的整个间隙。 金属栅极电极层和半导体栅极电极层之间的界面在该至少一个半导体鳍片上连续地延伸，并且不在至少一个半导体鳍片的任何一个之下。 在栅电极的图形化期间，由于半导体栅极电极层不存在于至少一个半导体鳍片之下，所以能够促进半导体栅极电极层中的半导体材料的去除。

公开(公告)号：US20140312420A1

公开(公告)日：2014-10-23

申请号：US14029306

申请日：2013-09-17

Applicant: International Business Machines Corporation

Inventor： Thomas N. Adam ,  Veeraraghavan S. Basker ,  Jinghong Li ,  Chung-Hsun Lin ,  Sebastian Naczas ,  Alexander Reznicek ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.

Abstract translation: 形成从半导体材料部分延伸的多个半导体散热片，半导体材料部分位于绝缘体上半导体基板的绝缘体层顶部。 形成跨越每个半导体鳍片的栅极结构和相邻栅极间隔物。 每个半导体鳍片的部分被暴露。 然后通过从未被栅极结构和栅极间隔物覆盖的暴露的半导体材料部分形成外延半导体材料来合并半导体鳍片的露出部分。

公开(公告)号：US20140308806A1

公开(公告)日：2014-10-16

申请号：US14021165

申请日：2013-09-09

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Ryan M. Martin ,  Jeffrey W. Sleight

IPC: H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66795 ,  Y02P80/30

Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

Abstract translation: 可以使用锥形鳍式场效应晶体管来提供通道的增强的静电控制。 在绝缘体层上形成具有基本上垂直的侧壁表面的半导体鳍片和介电鳍片盖的叠层。 半导体鳍片的侧壁表面被具有锥形厚度轮廓的介电翅片帽的蚀刻残余物材料钝化，使得蚀刻残余物质的厚度随着与介电翅片盖的距离而减小。 使用包括各向同性蚀刻部件的蚀刻来去除蚀刻残留物并且物理地暴露半导体鳍片的侧壁的下部。 蚀刻横向蚀刻半导体鳍片并在底部形成锥形区域。 半导体鳍片的底部的减小的横向宽度允许更好地控制鳍状场效应晶体管的沟道。

公开(公告)号：US20140306286A1

公开(公告)日：2014-10-16

申请号：US13860136

申请日：2013-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Ryan M. Martin ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66795 ,  Y02P80/30

Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

公开(公告)号：US20140266254A1

公开(公告)日：2014-09-18

申请号：US14029585

申请日：2013-09-17

Applicant: International Business Machines Corporation

Inventor： Wilfried E.A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: G01B7/06

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

公开(公告)号：US20140217508A1

公开(公告)日：2014-08-07

申请号：US13967888

申请日：2013-08-15

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/861

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

公开(公告)号：US20140217364A1

公开(公告)日：2014-08-07

申请号：US13971974

申请日：2013-08-21

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleights

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66136 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/938

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract translation: 一方面，一种制造电子设备的方法包括以下步骤。 在SOI晶片上的堆叠中形成交替的器件和牺牲层系列。 将纳米线棒蚀刻到器件/牺牲层中，使得堆叠的第一部分中的每个器件层和堆叠的第二部分中的每个器件层具有源极区，漏极区和多个纳米线 通道连接源极区域和漏极区域。 从纳米线条之间移除牺牲层。 选择性地形成围绕堆叠的第一部分中的纳米线通道的共形栅极介电层，其用作纳米级FET晶体管的沟道区。 在堆叠的第一和第二部分中围绕纳米线通道形成栅极。

公开(公告)号：US08799848B1

公开(公告)日：2014-08-05

申请号：US13741490

申请日：2013-01-15

Applicant: International Business Machines Corporation

Inventor： Wilfried Ernest-August Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Hailing Wang ,  Richard Q. Williams

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F17/5036

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个翅片。 该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件（IOFF），并且确定用于关断finFET器件（VOFF）的电压模型 ）。 该方法还包括将FinFET模型拟合到VOFF。