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    JOSEPHSON JUNCTION WITH SPACER
    1.
    发明申请
    JOSEPHSON JUNCTION WITH SPACER 有权
    JOSEPHSON连接与间距

    公开(公告)号：US20160211438A1

    公开(公告)日：2016-07-21

    申请号：US14597310

    申请日：2015-01-15

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L39/22 ,  H01L39/24 ,  H01L39/02

    CPC classification number: H01L39/223 ,  H01L39/2493

    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit may comprise: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.

    Abstract translation: 各种实施例针对被配置为充当约瑟夫逊结的电路。 电路可以包括：衬底上的结堆叠，所述结堆叠包括第一超导体电极的一部分，在第一超导体电极的顶侧上具有界面层，并且被配置为用作结叠层的隧道势垒。 电路还可以包括界面层顶部上的第二超导体电极的第一部分。 间隔物可以将结堆叠中的第一超导体电极的部分与第二超导体电极的第二超导电极的第二部分分离，其中第二超导体电极覆盖第一超导体电极。

    III-V finFETs on silicon substrate
    4.
    发明授权
    III-V finFETs on silicon substrate 有权
    硅衬底上的III-V finFET

    公开(公告)号：US08937299B2

    公开(公告)日：2015-01-20

    申请号：US13967102

    申请日：2013-08-14

    Applicant: International Business Machines Corporation

    Inventor： Anirban Basu ,  Cheng-Wei Cheng ,  Amlan Majumdar ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

    IPC: H01L29/78 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

    Abstract translation: 一种用于形成鳍状场效应晶体管的方法，包括在硅衬底上形成电介质层，在电介质层中形成高达纵横比的沟槽直至衬底，高纵横比包括大于或等于1:1的高宽比;以及 使用纵横比捕获工艺在沟槽中外延生长含硅的半导体材料以形成翅片。 蚀刻一个或多个电介质层以暴露鳍片的一部分。 在翅片的一部分上外延生长阻挡层，在鳍片上方形成栅叠层。 围绕翅片和门叠层的部分形成间隔件。 将掺杂剂植入翅片的部分。 源极和漏极区域使用非含硅半导体材料生长在翅片上。

    Josephson junction with spacer
    5.
    发明授权
    Josephson junction with spacer 有权

    公开(公告)号：US10170679B2

    公开(公告)日：2019-01-01

    申请号：US15786651

    申请日：2017-10-18

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L39/22 ,  H01L39/24

    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.

    Tapered fin field effect transistor
    6.
    发明授权
    Tapered fin field effect transistor 有权
    锥形场效应晶体管

    公开(公告)号：US09018084B2

    公开(公告)日：2015-04-28

    申请号：US14021165

    申请日：2013-09-09

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306

    CPC classification number: H01L29/7853 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66795 ,  Y02P80/30

    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

    Abstract translation: 可以使用锥形鳍式场效应晶体管来提供通道的增强的静电控制。 在绝缘体层上形成具有基本上垂直的侧壁表面的半导体鳍片和介电鳍片盖的叠层。 半导体鳍片的侧壁表面被具有锥形厚度轮廓的介电翅片帽的蚀刻残余物材料钝化，使得蚀刻残余物质的厚度随着与介电翅片盖的距离而减小。 使用包括各向同性蚀刻部件的蚀刻来去除蚀刻残留物并且物理地暴露半导体鳍片的侧壁的下部。 蚀刻横向蚀刻半导体鳍片并在底部形成锥形区域。 半导体鳍片的底部的减小的横向宽度允许更好地控制鳍状场效应晶体管的沟道。

    TAPERED FIN FIELD EFFECT TRANSISTOR
    7.
    发明申请
    TAPERED FIN FIELD EFFECT TRANSISTOR 有权
    锥形场效应晶体管

    公开(公告)号：US20140308806A1

    公开(公告)日：2014-10-16

    申请号：US14021165

    申请日：2013-09-09

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L21/306

    CPC classification number: H01L29/7853 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66795 ,  Y02P80/30

    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

    Abstract translation: 可以使用锥形鳍式场效应晶体管来提供通道的增强的静电控制。 在绝缘体层上形成具有基本上垂直的侧壁表面的半导体鳍片和介电鳍片盖的叠层。 半导体鳍片的侧壁表面被具有锥形厚度轮廓的介电翅片帽的蚀刻残余物材料钝化，使得蚀刻残余物质的厚度随着与介电翅片盖的距离而减小。 使用包括各向同性蚀刻部件的蚀刻来去除蚀刻残留物并且物理地暴露半导体鳍片的侧壁的下部。 蚀刻横向蚀刻半导体鳍片并在底部形成锥形区域。 半导体鳍片的底部的减小的横向宽度允许更好地控制鳍状场效应晶体管的沟道。

    TAPERED FIN FIELD EFFECT TRANSISTOR
    8.
    发明申请
    TAPERED FIN FIELD EFFECT TRANSISTOR 审中-公开

    公开(公告)号：US20140306286A1

    公开(公告)日：2014-10-16

    申请号：US13860136

    申请日：2013-04-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7853 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66795 ,  Y02P80/30

    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

    Josephson junction with spacer
    9.
    发明授权
    Josephson junction with spacer 有权

    公开(公告)号：US09929334B2

    公开(公告)日：2018-03-27

    申请号：US14597310

    申请日：2015-01-15

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L39/22 ,  H01L39/24

    CPC classification number: H01L39/223 ,  H01L39/2493

    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.

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