公开(公告)号：US09269787B2

公开(公告)日：2016-02-23

申请号：US14755862

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L21/8222 ,  H01L29/66 ,  H01L29/08 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

公开(公告)号：US20160043203A1

公开(公告)日：2016-02-11

申请号：US14451716

申请日：2014-08-05

Applicant: International Business Machines Corporation

Inventor： Deborah A. Alperstein ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Keith J. Machia ,  Christa R. Willets

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 在包含第一端子的基板上形成第一半导体层。 在第一半导体层上形成蚀刻停止层，在蚀刻停止层上形成第二半导体层。 蚀刻第二半导体层以在第二半导体层上的蚀刻掩模的位置处限定第二端子。 选择包括蚀刻停止层的第一材料和包括第二半导体层的第二材料，使得第二半导体层的第二材料以比蚀刻停止层的第一材料更高的蚀刻速率蚀刻。 第一半导体层可以是用于形成双极结型晶体管的本征基极和非本征基极的基极层。

公开(公告)号：US09224841B2

公开(公告)日：2015-12-29

申请号：US14162403

申请日：2014-01-23

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Qizhi Liu ,  Edward J. Nowak

IPC: H01L31/111 ,  H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer. Between adjacent mandrels, an opening is formed that extends vertically through the dielectric cap layer and through multiple monocrystalline semiconductor layers into a semiconductor substrate. A portion of the opening within the substrate is expanded to form a trench. This trench undercuts the semiconductor layers and extends laterally below adjacent sidewall spacers on either side of the opening. The trench is then filled with an isolation layer, thereby forming a trench isolation region, and a sidewall image transfer process is performed using the sidewall spacers to form a pair of monocrystalline semiconductor fins above the trench isolation region.

Abstract translation: 公开了具有单晶半导体鳍片的半导体结构，其在半导体衬底中的沟槽隔离区域上方并且可以并入半导体器件中。 还公开了通过在电介质盖层上的心轴的相对侧上形成侧壁间隔来形成这种结构的方法。 在相邻的心轴之间形成开口，其垂直延伸穿过电介质盖层并通过多个单晶半导体层进入半导体衬底。 衬底内的开口的一部分被扩展以形成沟槽。 该沟槽底切半导体层，并且在开口两侧的相邻侧壁间隔物侧向延伸。 然后用隔离层填充沟槽，从而形成沟槽隔离区域，并且使用侧壁间隔物进行侧壁图像转印处理，以在沟槽隔离区域上方形成一对单晶半导体鳍片。

公开(公告)号：US20150364492A1

公开(公告)日：2015-12-17

申请号：US14834696

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/165 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

Abstract translation: 各种实施例包括场效应晶体管（FET）和相关的集成电路（IC）布局。 一个FET包括：包括一组沟槽的硅衬底; 邻接硅衬底的第一氧化物; 覆盖硅衬底的硅锗（SiGe）层; 覆盖SiGe层的硅层; 覆盖硅层的第二氧化物，其中硅层包括多个硅化物区域; 覆盖相邻自对准硅化物区域之间的第二氧化物的栅极结构; 以及接触所述栅极结构的第一接触; 接触一个所述自对准区域的第二接触点; 部分地填充该组沟槽并在覆盖SiGe层的硅层上方延伸的第三氧化物; 以及在所述一组沟槽中的每一个中的气隙，所述气隙由所述第三氧化物包围。

公开(公告)号：US20150363535A1

公开(公告)日：2015-12-17

申请号：US14304318

申请日：2014-06-13

Applicant: International Business Machines Corporation

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo ,  Steven M. Shank

IPC: G06F17/50 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12061

Abstract: Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a crystallographic direction to a crystallographic direction.

Abstract translation: 各种实施例包括局部在体硅衬底上的硅基光波导结构，以及用于通过修改集成电路（IC）设计结构来形成这种结构的系统和程序产品。 实施例包括实现在计算机实现的IC形成系统中准备用于形成IC设计结构的制造数据的过程，其中制造数据的准备包括将指令插入到制造数据中以将至少一种形状的边缘从 <110>结晶方向到<100>晶体方向。

公开(公告)号：US20150294973A1

公开(公告)日：2015-10-15

申请号：US14734310

申请日：2015-06-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Qizhi Liu ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/161 ,  H01L27/12

CPC classification number: H01L27/10826 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.

Abstract translation: 本公开通常提供具有体硅片finFET的集成电路（IC）结构及其形成方法。 根据本公开的IC结构可以包括：体基板; 位于所述本体衬底的第一区域上的鳍状物FET; 以及分层虚拟结构，其位于所述本体衬底的第二区域上，其中所述分层虚拟结构包括第一晶体半导体层，位于所述第一晶体半导体层上的第二晶体半导体层，其中所述第一晶体半导体层包括不同的材料 以及位于所述第二晶体半导体层上的第三晶体半导体层，其中所述第三晶体半导体层包括与所述第二晶体半导体层不同的材料。

公开(公告)号：US20150228769A1

公开(公告)日：2015-08-13

申请号：US14694359

申请日：2015-04-23

Applicant: International Business Machines Corporation

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo

IPC: H01L29/737 ,  H01L29/16 ,  H01L29/08 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/737 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Ccb and collector resistance Rc are minimized within the resulting bipolar semiconductor device.

公开(公告)号：US20150214344A1

公开(公告)日：2015-07-30

申请号：US14677303

申请日：2015-04-02

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Abstract translation: 双极结型晶体管的器件结构，设计结构和制造方法。 由包含第一半导体材料的第一层和由第二半导体材料构成的第二层设置在包含双极结型晶体管的第一端子的衬底上。 第二层设置在第一层上，并且在第二层上形成图案化的蚀刻掩模。 沟槽延伸穿过图案硬掩模层，第一层和第二层并进入衬底。 沟槽限定了与第二层的一部分堆叠的第一层的一部分。 使用选择性蚀刻工艺来相对于第一层的截面来缩小第二层的截面以限定第二端子并且加宽衬底中的沟槽的一部分以削弱第一层的部分。

公开(公告)号：US08999804B2

公开(公告)日：2015-04-07

申请号：US13887640

申请日：2013-05-06

Applicant: International Business Machines Corporation

Inventor： Qizhi Liu

IPC: H01L21/331 ,  H01L21/762 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L29/735 ,  G06F17/5045 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/1008 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/73

Abstract: Fabrication methods for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference.

Abstract translation: 双极结型晶体管的制造方法。 在基板上形成半导体材料层，在半导体材料层上形成掩模层。 将掩模层图案化以形成到半导体材料层的多个开口。 在掩模层形成和图案化之后，半导体材料层在开口的相应位置被蚀刻以限定第一沟槽，第二沟槽通过半导体材料层的第一部分与第一沟槽分开，该第二部分界定了双极的端子 以及通过半导体材料层的限定隔离基座的第二部分与第一沟槽分离的第三沟槽。 在衬底中的至少部分地使用隔离基座作为位置参考确定的位置处形成沟槽隔离区域。

公开(公告)号：US20150069571A1

公开(公告)日：2015-03-12

申请号：US14024075

申请日：2013-09-11

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide.

Abstract translation: 根据本文的结构，硅衬底在硅衬底中具有有源器件。 电介质膜位于有源器件上。 绝缘膜位于有源器件周围的绝缘膜中。 沟槽延伸穿过介电膜并至少部分地进入硅衬底。 核心在隔离槽。 核心包括具有大于二氧化硅的热导率和大致等于二氧化硅的导电性的材料。