公开(公告)号：US06171891B2

公开(公告)日：2001-01-09

申请号：US09031653

申请日：1998-02-27

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu ,  Tiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Tiaw-Ren Shih

IPC: H01L21336

CPC classification number: H01L29/7833 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/1083

Abstract: A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Abstract translation: 用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。 在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。 在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。 在栅极堆叠的侧壁上形成间隔物。 然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。 形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。

公开(公告)号：US5939756A

公开(公告)日：1999-08-17

申请号：US891379

申请日：1997-07-11

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L27/02 ,  H01L29/72

CPC classification number: H01L27/0266 ,  H01L27/0259

Abstract: An apparatus and method are disclosed for enhancing the operation of ESD protective circuits in a VLSI chip with a plurality of parallel CMOS devices therein, particularly a plurality of NMOS devices arranged as parallel N-P-N bipolars. In the MOSFET circuits, a number of sets of cooperating N+ regions are deposited in a P-well in a P-type substrate to form, with electrodes and connections, a set of parallel source-base-drain transistors. The ESD pass voltage is effected by different processes due to the current-crowding effect. The current distribution in each of the N-P-N bipolars is strongly dependent on the P-well resistivity so that to reduce the current crowding effect and render the current distribution uniform in each parallel N-P-N bipolar, an additional P-well implantation is used to reduce the P-well resistivity in the input, I/O, and output buffer ESD protection circuits. Accordingly, the effective protection width will be increased and the ESD performance is improved.

Abstract translation: 公开了一种用于增强其中具有多个并联CMOS器件的VLSI芯片中的ESD保护电路的操作的装置和方法，特别是排列成并行N-P-N双极的多个NMOS器件。 在MOSFET电路中，多个配合的N +区组被沉积在P型衬底中的P阱中，以形成一组平行的源极 - 基极 - 漏极晶体管，其中电极和连接形成一组平行的源极 - 基极 - 漏极晶体管。 由于电流拥挤效应，ESD通过电压由不同的工艺实现。 每个NPN双极中的电流分布强烈依赖于P阱电阻率，以便减少电流拥挤效应并使电流分布在每个并联的NPN双极中均匀，使用附加的P阱注入来减少P - 输入，I / O和输出缓冲器ESD保护电路中的电阻率。 因此，有效的保护宽度将增加并且ESD性能得到改善。

公开(公告)号：US5913122A

公开(公告)日：1999-06-15

申请号：US789717

申请日：1997-01-27

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Jung-Ke Yeh ,  Hsiu-Han Liao

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Jung-Ke Yeh ,  Hsiu-Han Liao

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/66575 ,  H01L27/0928 ,  H01L29/0847

Abstract: An FET semiconductor device comprises a doped silicon semiconductor substrate having surface. The substrate being doped with a first type of dopant. An N-well is formed within the surface of the P-substrate. A P-well is formed within the N-well forming a twin well. Field oxide regions are formed on the surface of the substrate located above borders between the wells and regions of the substrate surrounding the wells. A gate electrode structure is formed over the P-well between the field oxide regions. A source region and a drain region are formed in the surface of the substrate. The source region and the drain region are self-aligned with the gate electrode structure with the source region and the drain region being spaced away from the field oxide regions by a gap of greater than or equal to about 0.7 .mu.m.

Abstract translation: FET半导体器件包括具有表面的掺杂硅半导体衬底。 衬底被掺杂有第一类型的掺杂剂。 在P基板的表面内形成有N阱。 在形成双井的N阱内形成P阱。 位于位于井周围的边界之上的基板的表面上的场氧化物区域和围绕所述孔的基板的区域形成。 在场氧化物区域之间的P阱上形成栅电极结构。 源极区域和漏极区域形成在衬底的表面中。 源极区域和漏极区域与栅极电极结构自对准，源极区域和漏极区域与场氧化物区域间隔开大于或等于约0.7μm的间隙。

公开(公告)号：US5811856A

公开(公告)日：1998-09-22

申请号：US554994

申请日：1995-11-13

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0251 ,  H01L2924/0002

Abstract: An object of this invention is the creation of an input protection circuit for highly dense integrated circuits that has improved ESD immunity. This is accomplished by the addition of a P.sup.+ diffusion adjacent to the emitter of a field device to make the base resistance of each of the field devices approximately equal. When an ESD source is contacted to the input protection circuit, the field devices will conduct simultaneously and with equal currents, thus preventing high current densities that can cause circuit failure.

Abstract translation: 本发明的目的是为具有改进的ESD抗扰度的高密度集成电路的创建输入保护电路。 这是通过在现场设备的发射极附近添加P +扩散来实现的，以使每个现场设备的基极电阻近似相等。 当ESD源与输入保护电路接触时，现场设备将以同等电流同时传导，从而防止可能导致电路故障的高电流密度。

公开(公告)号：US5659245A

公开(公告)日：1997-08-19

申请号：US658524

申请日：1996-06-03

Applicant: King-Ho Ping ,  Jian-Hsing Lee

Inventor： King-Ho Ping ,  Jian-Hsing Lee

IPC: G01R1/18 ,  G01R31/28 ,  H05K1/02 ,  H05K3/00 ,  H05K9/00 ,  G01R31/02

CPC classification number: G01R31/2863 ,  G01R1/18 ,  H05K1/0218 ,  H05K1/0259 ,  H05K9/0067 ,  H05K1/0215 ,  H05K2201/09354 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K3/0061

Abstract: A burn-in board assembly for the protection of integrated circuit modules from Electrostatic discharge and the shielding of said integrated circuit modules from Electromagnetic Interference during said electrostatic discharge is described. The burn-in board assembly has a printed circuit board onto which the integrated circuits are mounted by soldering or plugging into sockets soldered to said burnin board assembly. Disposed upon the printed circuit board is a plurality of input stimuli, feedback sensing, and output response signal traces to connect the integrated circuit modules to a connector that is coupled to a input stimulus generator and feedback sensing and output response monitor. Also disposed upon the printed circuit board is a plurality of ground traces and voltage supply traces to connect the integrated circuit modules to the connector that is coupled to a voltage supply source and the system ground reference point. An electrostatic discharge bypass track is disposed peripherally upon the printed circuit board and is connected to the ground reference point through the connector to prevent damage to the printed circuit modules during an electrostatic discharge event. A first and a second electromagnetic interference shielding trace is disposed upon the printed circuit board. Each electromagnetic shielding trace is connected at opposite ends to the ground reference point through the connector to shield the printed circuit traces from the effects of the electromagnetic interference.

Abstract translation: 描述了一种用于在静电放电期间保护集成电路模块免受静电放电和屏蔽所述集成电路模块与电磁干扰的老化板组件。 老化板组件具有印刷电路板，集成电路通过焊接或插入到焊接到所述燃烧板组件的插座中而安装在该印刷电路板上。 布置在印刷电路板上的是多个输入刺激，反馈感测和输出响应信号迹线，以将集成电路模块连接到耦合到输入激励发生器和反馈感测和输出响应监视器的连接器。 还布置在印刷电路板上的是多个接地迹线和电压提供迹线，用于将集成电路模块连接到耦合到电压源和系统接地参考点的连接器。 静电放电旁路轨道周边布置在印刷电路板上，并通过连接器连接到接地参考点，以防止在静电放电事件期间损坏印刷电路模块。 第一和第二电磁干扰屏蔽迹线设置在印刷电路板上。 每个电磁屏蔽迹线通过连接器在相对端连接到接地参考点，以屏蔽印刷电路迹线免受电磁干扰的影响。

公开(公告)号：US20150079755A1

公开(公告)日：2015-03-19

申请号：US14559542

申请日：2014-12-03

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/66

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract translation: 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US08928078B2

公开(公告)日：2015-01-06

申请号：US13726579

申请日：2012-12-25

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract translation: 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US20140175545A1

公开(公告)日：2014-06-26

申请号：US13726579

申请日：2012-12-25

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract translation: 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US08194371B2

公开(公告)日：2012-06-05

申请号：US12419608

申请日：2009-04-07

Applicant: Chin-Hsin Tang ,  Jian-Hsing Lee

Inventor： Chin-Hsin Tang ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H01L27/0207 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.

Abstract translation: 提供半导体器件。 在一个实施例中，半导体器件包括反相器。 反相器耦合到NMOS器件。 NMOS器件可以是保护逆变器免受充电效应和/或等离子体引起的损坏的保护装置。 NMOS器件可以耦合到电源（例如，Vss）。 NMOS器件可以进一步耦合到电容器。 电容器的电荷可以将通过NMOS器件的电流放电到电源。

公开(公告)号：US20100254050A1

公开(公告)日：2010-10-07

申请号：US12419608

申请日：2009-04-07

Applicant: Chin-Hsin Tang ,  Jian-Hsing Lee

Inventor： Chin-Hsin Tang ,  Jian-Hsing Lee

IPC: H02H9/04 ,  H01L27/06 ,  H01L21/02

CPC classification number: H01L27/0207 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.

Abstract translation: 提供半导体器件。 在一个实施例中，半导体器件包括反相器。 反相器耦合到NMOS器件。 NMOS器件可以是保护逆变器免受充电效应和/或等离子体引起的损坏的保护装置。 NMOS器件可以耦合到电源（例如，Vss）。 NMOS器件可以进一步耦合到电容器。 电容器的电荷可以将通过NMOS器件的电流放电到电源。