公开(公告)号：US20090279341A1

公开(公告)日：2009-11-12

申请号：US12115989

申请日：2008-05-06

申请人： Craig S. Forrest ,  Robert J. Drost ,  Ronald Ho ,  Ivan E. Sutherland

发明人： Craig S. Forrest ,  Robert J. Drost ,  Ronald Ho ,  Ivan E. Sutherland

IPC分类号： G11C5/06

CPC分类号： G11C5/04 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1054 ,  G11C7/1078 ,  G11C7/1081 ,  H01L23/48 ,  H01L23/642 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/167 ,  H01L2225/06562 ,  H01L2924/01067 ,  H01L2924/14 ,  H01L2924/19041

摘要： A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.

摘要翻译： 存储器模块由多个存储器芯片和固定在基板上的光学接口芯片形成。 芯片通过邻近通信（PxC）相互连接，其中每个芯片包括发射和接收元件，例如当芯片彼此面对放置在一起时形成电容耦合链路的电焊盘。 PxC链路可以直接在芯片之间或通过中间无源桥芯片。 接口芯片耦合到外部光通道并且包括用于与存储器芯片通信的光学和电信号之间的转换器，控制电路，缓冲器和PxC元件。 存储器阵列可以是形成冗余PxC网络的接口芯片周围的线性或二维阵列，可选地具有冗余PxC连接。 多个矩形存储器芯片可以将它们的窄边呈现给接口芯片以最大化带宽。

公开(公告)号：US20090269884A1

公开(公告)日：2009-10-29

申请号：US12498282

申请日：2009-07-06

申请人： Robert J. Drost ,  Gary R. Lauterbach ,  Danny Cohen

发明人： Robert J. Drost ,  Gary R. Lauterbach ,  Danny Cohen

IPC分类号： H01L21/98

CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49133 ,  Y10T29/49169 ,  H01L2924/00

摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.

摘要翻译： 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。 该系统还包括具有主动面的集成电路芯片，有源电路和信号焊盘所在的面以及与主动面相对的背面。 此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。

公开(公告)号：US07573720B1

公开(公告)日：2009-08-11

申请号：US11154392

申请日：2005-06-15

申请人： Robert J. Drost ,  Gary R. Lauterbach ,  Danny Cohen

发明人： Robert J. Drost ,  Gary R. Lauterbach ,  Danny Cohen

IPC分类号： H05K7/00

CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49133 ,  Y10T29/49169 ,  H01L2924/00

摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.

摘要翻译： 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。 该系统还包括具有主动面的集成电路芯片，有源电路和信号焊盘所在的面以及与主动面相对的背面。 此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。

公开(公告)号：US07483248B1

公开(公告)日：2009-01-27

申请号：US11134799

申请日：2005-05-19

申请人： Ronald Ho ,  Robert J. Drost ,  Arthur R. Zingher

发明人： Ronald Ho ,  Robert J. Drost ,  Arthur R. Zingher

IPC分类号： H02H3/00 ,  H02H3/08 ,  H02H9/02 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06 ,  H01C7/12 ,  G01R15/18

CPC分类号： G01R19/16552

摘要： One embodiment of the present invention provides a system that detects changes in power-supply current within an integrated circuit (IC) chip. During operation, the system monitors an induced current through a detection loop. This detection loop is situated at least partially within the IC chip in close proximity to a power-supply current for the IC chip, so that a change in the power-supply current changes a magnetic field passing through the detection loop, thereby inducing a corresponding current through the detection loop. The system then generates a control signal based on the induced current, so that changes in the power-supply current cause the control signal to change. In addition, the system uses the control signal to control circuits within the IC chip.

摘要翻译： 本发明的一个实施例提供一种检测集成电路（IC）芯片内的电源电流的变化的系统。 在运行期间，系统通过检测回路监测感应电流。 该检测环路至少部分地位于IC芯片内，与IC芯片的电源电流接近，使得电源电流的变化改变通过检测环路的磁场，从而引起对应的 电流通过检测回路。 然后，该系统基于感应电流产生控制信号，使得电源电流的变化导致控制信号改变。 此外，该系统使用控制信号来控制IC芯片内的电路。

公开(公告)号：US20090013214A1

公开(公告)日：2009-01-08

申请号：US11773020

申请日：2007-07-03

申请人： Frankie Y. Liu ,  Ronald Ho ,  Robert J. Drost

发明人： Frankie Y. Liu ,  Ronald Ho ,  Robert J. Drost

IPC分类号： G06F11/00

CPC分类号： G01R31/31705 ,  G01R19/0053 ,  G01R31/2884

摘要： Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.

摘要翻译： 描述包括调试电路的集成电路的实施例。 该调试电路被配置为通过对与异步电路相关联的异步信号执行模拟测量来测试异步电路，并且包括被配置为基于一个或多个异步信号门控调试电路的触发模块。 该触发模块具有连续的操作模式和单次操作模式。 调试电路内的定时模块具有超过预定值的定时范围，并且被配置为提供对应于第一时基的信号或对应于第二时基的信号。 此外，调试电路内的控制逻辑被配置为选择作为第一时基或第二时基的调试电路的操作模式和给定时基。

公开(公告)号：US07460035B1

公开(公告)日：2008-12-02

申请号：US11773181

申请日：2007-07-03

申请人： Ronald Ho ,  Danny Cohen ,  Robert J. Drost

发明人： Ronald Ho ,  Danny Cohen ,  Robert J. Drost

IPC分类号： H03M5/00

CPC分类号： H03M5/12

摘要： Embodiments of an encoding circuit to communicate a sequence of words are described. This encoding circuit includes an encoding module that is configured to receive a first sequence of words and to generate a DC-balanced second sequence of words based on the first sequence of words, where communicating the second sequence of words consumes less energy than communicating a third sequence of words that includes words in the first sequence of words alternating with words in the inverse of the first sequence of words. In addition, the second sequence of words includes substantially twice as many words as the first sequence of words.

摘要翻译： 描述用于传送字序列的编码电路的实施例。 该编码电路包括编码模块，其被配置为接收第一个单词序列，并且基于第一个单词序列生成直流平衡的第二个单词序列，其中传达第二个单词序列的消耗比传送第三个单词的能量少 单词序列包括第一个单词序列中的单词与第一个单词序列中的单词交替出现的单词。 另外，第二个词序列包括基本上是第一个词序列的两倍的单词。

公开(公告)号：US07453882B2

公开(公告)日：2008-11-18

申请号：US10927285

申请日：2004-08-25

申请人： Ronald Ho ,  Jonathan K. Gainsley ,  Robert J. Drost

发明人： Ronald Ho ,  Jonathan K. Gainsley ,  Robert J. Drost

IPC分类号： H04L12/28 ,  G06F3/00

CPC分类号： G06F13/4286

摘要： One embodiment of the present invention provides a system that asynchronously controls the sending of data items from a sender to a receiver. The system includes a data path between the sender and the receiver, a first control path between the sender and the receiver, and a second control path between the sender and the receiver. The first control path and the second control path alternately control the asynchronous transmission of consecutive data items on the data path between the sender and the receiver.

摘要翻译： 本发明的一个实施例提供了一种异步地控制从发送者到接收者的数据项的发送的系统。 该系统包括发送器和接收器之间的数据路径，发送器和接收器之间的第一控制路径以及发送器和接收器之间的第二控制路径。 第一控制路径和第二控制路径交替地控制发送方和接收方之间的数据路径上的连续数据项的异步传输。

公开(公告)号：US20080208521A1

公开(公告)日：2008-08-28

申请号：US12114404

申请日：2008-05-02

申请人： Robert J. Drost ,  Ivan E. Sutherland ,  William S. Coates

发明人： Robert J. Drost ,  Ivan E. Sutherland ,  William S. Coates

IPC分类号： G01C9/00

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2224/0401

摘要： Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

摘要翻译： 本发明的实施例提供了一种系统，其将面对面地定位在不同半导体芯片上的迷你条电子对准以便于通过电容耦合来促进半导体芯片之间的通信。 在操作期间，系统在第一芯片上选择一组发射机迷你条来形成发射机位位置，并在第二芯片上选择一组接收器迷你条来形成接收器位位置。 然后，系统将第一芯片上的发送器位置与第二芯片上的接收器位置相关联。 以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

公开(公告)号：US07417993B1

公开(公告)日：2008-08-26

申请号：US10742075

申请日：2003-12-18

申请人： Josephus C. Ebergen ,  Ivan E. Sutherland ,  Robert J. Drost

发明人： Josephus C. Ebergen ,  Ivan E. Sutherland ,  Robert J. Drost

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L1/00

CPC分类号： H04L49/901 ,  H04L49/90

摘要： One embodiment of the present invention provides a system for high-throughput asynchronous communication that includes a sender and a receiver. A sender's first-in, first-out (FIFO) buffer is coupled to an input of the sender, a receiver's FIFO buffer is coupled to an input of the receiver, a forward communication channel is coupled between the sender and the receiver's FIFO buffer, and a reverse communication channel is coupled between the receiver and the sender's FIFO buffer. The forward communication channel, the receiver's FIFO buffer, the reverse communication channel, and the sender's FIFO buffer operate collectively as a network FIFO between the sender and the receiver. The network FIFO is configured to ensure that asynchronous communication between the sender and the receiver takes place reliably and without unnecessary waiting by the sender or the receiver.

摘要翻译： 本发明的一个实施例提供一种包括发送器和接收器的用于高吞吐量异步通信的系统。 发送方的先进先出（FIFO）缓冲器耦合到发送方的输入，接收器的FIFO缓冲器耦合到接收器的输入，前向通信信道耦合在发送方和接收方的FIFO缓冲器之间， 并且反向通信信道耦合在接收器和发送器的FIFO缓冲器之间。 前向通信信道，接收机的FIFO缓冲区，反向通信信道和发送方的FIFO缓冲区共同作为发送方和接收方之间的网络FIFO进行操作。 网络FIFO被配置为确保发送器和接收器之间的异步通信可靠地发生，并且不需要由发送器或接收器等待。

公开(公告)号：US20080159412A1

公开(公告)日：2008-07-03

申请号：US11647060

申请日：2006-12-27

申请人： Robert J. Drost

发明人： Robert J. Drost

IPC分类号： H04B3/04

CPC分类号： H04L25/0284 ,  H04L25/026

摘要： An integrated circuit containing a communication channel is described. This communication channel includes: a transmit circuit configured to transmit signals; a link coupled to an output of the transmit circuit; a receive circuit coupled to the link; and a clamping circuit coupled to the link. Note that the transmit circuit is capacitively coupled to the receive circuit via the link. Furthermore, the clamping circuit is configured to compensate for leakage current on the link by maintaining a voltage on the link corresponding to a logical “1” or a logical “0.” This voltage is based on a history of the transmitted signals.

摘要翻译： 描述包含通信信道的集成电路。 该通信信道包括：发送电路，被配置为发送信号; 耦合到所述发射电路的输出的链路; 耦合到所述链路的接收电路; 以及耦合到所述链路的钳位电路。 注意，发送电路经由链路电容耦合到接收电路。 此外，钳位电路被配置为通过维持对应于逻辑“1”或逻辑“0”的链路上的电压来补偿链路上的泄漏电流。 该电压基于发送信号的历史。