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公开(公告)号：US07525199B1
公开(公告)日：2009-04-28
申请号：US10851835
申请日：2004-05-21
申请人： Gary R. Lauterbach , Danny Cohen , Robert J. Drost
发明人： Gary R. Lauterbach , Danny Cohen , Robert J. Drost
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L24/73 , H01L25/0652 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15153 , H01L2924/00012 , H01L2924/00
摘要： A plurality of integrated circuit packages are disposed on a substrate. The plurality of integrated circuit packages includes a first type of integrated circuit package that has an inactive side facing the substrate and an active side facing away from the substrate. The plurality of integrated circuit packages also includes a second type of integrated circuit package that has an inactive side facing away from the substrate and an active side facing the substrate. The first type of integrated circuit package and the second type of integrated circuit package are disposed such that a proximity communication enabled portion of the first type of integrated circuit package is aligned with a proximity communication enabled portion of the second type of integrated circuit package.
摘要翻译： 多个集成电路封装设置在基板上。 多个集成电路封装包括第一类型的集成电路封装，其具有面向基板的无效侧和远离基板的有源侧。 多个集成电路封装还包括第二类型的集成电路封装，其具有背离衬底的无效侧和面向衬底的有源侧。 第一类型的集成电路封装和第二类型的集成电路封装被布置成使得第一类型的集成电路封装的邻近通信使能部分与第二类型的集成电路封装的接近通信使能部分对准。
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2.发明授权Method for manufacturing an active socket for facilitating proximity communication 有权用于制造用于促进邻近通信的有源插座的方法公开(公告)号：US08166644B2
公开(公告)日：2012-05-01
申请号：US12498282
申请日：2009-07-06
申请人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
发明人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
IPC分类号： H05K3/30
CPC分类号： H01L23/48 , H01L25/0652 , H01L2225/06527 , H01L2225/06589 , H01L2924/0002 , H01L2924/3011 , Y10T29/49133 , Y10T29/49169 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.
摘要翻译： 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。 该系统还包括集成电路芯片，其具有有源电路和信号焊盘所在的有源面以及与有源面相对的背面。 此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。
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公开(公告)号：US20090269884A1
公开(公告)日：2009-10-29
申请号：US12498282
申请日：2009-07-06
申请人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
发明人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
IPC分类号： H01L21/98
CPC分类号： H01L23/48 , H01L25/0652 , H01L2225/06527 , H01L2225/06589 , H01L2924/0002 , H01L2924/3011 , Y10T29/49133 , Y10T29/49169 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.
摘要翻译： 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。 该系统还包括具有主动面的集成电路芯片，有源电路和信号焊盘所在的面以及与主动面相对的背面。 此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。
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公开(公告)号：US07573720B1
公开(公告)日：2009-08-11
申请号：US11154392
申请日：2005-06-15
申请人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
发明人： Robert J. Drost , Gary R. Lauterbach , Danny Cohen
IPC分类号： H05K7/00
CPC分类号： H01L23/48 , H01L25/0652 , H01L2225/06527 , H01L2225/06589 , H01L2924/0002 , H01L2924/3011 , Y10T29/49133 , Y10T29/49169 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.
摘要翻译： 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。 该系统还包括具有主动面的集成电路芯片，有源电路和信号焊盘所在的面以及与主动面相对的背面。 此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。
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公开(公告)号：US07170121B1
公开(公告)日：2007-01-30
申请号：US11241599
申请日：2005-09-29
IPC分类号： H01L29/76 , H01L29/768 , H03K19/0175
CPC分类号： H03K17/945 , H03K2217/94089
摘要： One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.
摘要翻译： 本发明的一个实施例提供了一种接近I / O开关，其被配置为在计算机系统中的组件之间传送数据。 该接近I / O开关由多个开关芯片组成，它们通过电容耦合耦合在一起。 这使得多个开关芯片能够彼此通信，而不受传统的非电容通信机制的限制。 接近I / O开关中的多个开关芯片还被配置为通过传统的非电容通信机制与计算机系统中的组件进行通信。
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6.发明授权Integrated circuit assembly module that supports capacitive communication between semiconductor dies 有权集成电路组件模块，支持半导体管芯之间的电容连接公开(公告)号：US06870271B2
公开(公告)日：2005-03-22
申请号：US10671642
申请日：2003-09-26
IPC分类号： H01L25/18 , H01L23/367 , H01L23/473 , H01L23/48 , H01L25/04 , H01L25/065 , H01L23/52 , H05K7/00
CPC分类号： H01L23/48 , H01L23/367 , H01L23/473 , H01L25/0652 , H01L2225/06513 , H01L2225/06534 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The first and second semiconductor dies are positioned face-to-face within the assembly module so that signal pads on the first semiconductor die overlap with signal pads on the second semiconductor die, thereby facilitating capacitive communication between the first and second semiconductor dies. Additionally, the first and second semiconductor dies are pressed together between a first substrate and a second substrate so that a front side of the first substrate is in contact with the back face of the first semiconductor die and a front side of the second substrate is in contact with the back face of the second semiconductor die.
摘要翻译： 本发明的一个实施例提供了一种集成电路组件模块，其包括第一半导体管芯和第二半导体管芯，每个具有有源面的半导体管芯具有有源电路和信号焊盘的位置以及与该有源面相对的背面。 第一和第二半导体管芯在组件模块内面对面地定位，使得第一半导体管芯上的信号焊盘与第二半导体管芯上的信号焊盘重叠，从而有助于第一和第二半导体管芯之间的电容连通。 此外，第一和第二半导体管芯在第一基板和第二基板之间被压在一起，使得第一基板的前侧与第一半导体管芯的背面接触，并且第二基板的前侧处于 与第二半导体管芯的背面接触。
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公开(公告)号：US06958538B1
公开(公告)日：2005-10-25
申请号：US10983250
申请日：2004-11-04
CPC分类号： G06F15/17375 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.
摘要翻译： 本发明的一个实施例提供了一种接近I / O开关，其被配置为在计算机系统中的组件之间传送数据。 该接近I / O开关由多个开关芯片组成，它们通过电容耦合耦合在一起。 这使得多个开关芯片能够彼此通信，而不受传统的非电容通信机制的限制。 接近I / O开关中的多个开关芯片还被配置为通过传统的非电容通信机制与计算机系统中的组件进行通信。
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8.发明授权Microprocessor configured to generate help instructions for performing data cache fills 失效微处理器被配置为生成用于执行数据缓存填充的帮助指令
公开(公告)号：US5878252A
公开(公告)日：1999-03-02
申请号：US884065
申请日：1997-06-27
CPC分类号： G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/3816 , G06F9/3824 , G06F9/3828 , G06F9/3836
摘要： A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction. The bypass help instruction causes the datum requested by the miss instruction to be forwarded to the destination of the miss instruction.
摘要翻译： 微处理器被配置为响应于数据高速缓存未命中产生帮助指令。 帮助指令以类似于导致未命中的指令（“未命令指令”）的方式流过微处理器的指令处理流水线。 帮助指令使用miss指令的源操作数来形成未命中地址，从而使用用于计算缓存访问地址的相同元素来提供填充地址。 在一个实施例中，生成填充帮助指令和旁路帮助指令。 填充帮助指令在填充数据到达的时钟周期期间向数据高速缓存提供输入地址。 由此选择数据高速缓存的适当行以存储填充数据。 旁路帮助指令被调度到不同于填充帮助指令占据的阶段的第二流水线阶段。 旁路帮助指令导致由miss指令请求的数据被转发到未命中指令的目的地。
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公开(公告)号：US4111272A
公开(公告)日：1978-09-05
申请号：US748397
申请日：1976-12-07
CPC分类号： G05D7/0605 , G05D7/0611
摘要： Disclosed herein is an automatically controlled weigh feeding apparatus including a container for prefilling with a substance, a device for discharging the substance from the container at a controllable rate, apparatus for weighing the substance being discharged and for producing an electrical signal proportional to that weight, a voltage to frequency converter connected to receive the electrical signals, a digital computer, apparatus coupled to an output of the voltage to frequency converter for inputting data signals to the digital computer, the computer being adapted to compute a corrective signal based on the input data signals received, and coupling apparatus coupled between the computer and the device for discharging the substance from the container for controlling the rate of discharge responsive to the corrective signal.
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公开(公告)号：US07783786B1
公开(公告)日：2010-08-24
申请号：US10801456
申请日：2004-03-16
申请人： Gary R. Lauterbach
发明人： Gary R. Lauterbach
IPC分类号： G06F15/16
CPC分类号： H04L67/1095
摘要： A system comprising a first node and a second node located in a single multiprocessor system, the first node including a first router and a first replicated service executing on a first operating system, the second node including a second router and a second replicated service executing on a second operating system, and a mesh interconnect connecting the first node to the second node using the first router and the second router.
摘要翻译： 一种包括位于单个多处理器系统中的第一节点和第二节点的系统，所述第一节点包括在第一操作系统上执行的第一路由器和第一复制服务，所述第二节点包括第二路由器和第二复制服务 第二操作系统以及使用第一路由器和第二路由器将第一节点连接到第二节点的网状互连。
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