公开(公告)号：US6055289A

公开(公告)日：2000-04-25

申请号：US593493

申请日：1996-01-30

申请人： Jeffrey P. Wright ,  Hua Zheng

发明人： Jeffrey P. Wright ,  Hua Zheng

IPC分类号： H03K21/00 ,  H03K21/08

CPC分类号： H03K21/00

摘要： A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

摘要翻译： 共享计数器在诸如存储器集成电路的电子电路中执行多个计数功能。 输入选择电路在给定时间选择M个输入数据组中的一个作为计数器初始化数据提供。 计数器电路基于计数器初始化数据提供计数器输出数据。 输出电路将计数器输出数据提供给电子电路中的K个目标电路。 输出电路在给定时间内仅提供K个目标电路中的一个与计数器输出数据。

公开(公告)号：US6011742A

公开(公告)日：2000-01-04

申请号：US915312

申请日：1997-08-20

申请人： Hua Zheng

发明人： Hua Zheng

IPC分类号： G11C7/06 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C29/789 ,  G11C29/781 ,  G11C7/067

摘要： A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry. A transistor having a large channel resistance, however, is placed within a feedback path of the latch. Therefore, after the latch is set, if the antifuse cell is blown, the high resistance transistor provides a resistive current path from the V.sub.CC to ground.

摘要翻译： 单个上拉电路在冗余行反熔丝电池和冗余列反熔丝电池之间共享。 此外，在两个反熔丝电池之间共享单个选择电路。 提供给它的行选择信号选择用于冗余行的反熔断电池，而列选择信号选择用于冗余列的反冒点电池。 在锁存电路内采用小通道长度的晶体管。 结果，当反熔丝电池不被熔断时，锁存器可以快速上拉一个值，并且由于锁存器的RC时间常数减小，所以锁存器内的值快速地锁存在锁存器内。 使用具有非常短的持续时间的脉冲上拉信号来使能锁存器。 由于脉冲上拉信号具有短的持续时间，所以通过锁存器和吹制的反熔丝电池提供高电压电源VCC以短时间接地，从而最小化这种低电阻电流路径损坏电路的可能性 。 然而，具有大的沟道电阻的晶体管被​​放置在锁存器的反馈路径内。 因此，在锁存器被置位之后，如果反熔丝电池被熔断，则高电阻晶体管提供从VCC到地的电阻电流路径。

公开(公告)号：US5999481A

公开(公告)日：1999-12-07

申请号：US918614

申请日：1997-08-22

申请人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

发明人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.

公开(公告)号：US5978298A

公开(公告)日：1999-11-02

申请号：US156098

申请日：1998-09-17

申请人： Hua Zheng

发明人： Hua Zheng

IPC分类号： G11C7/06 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/789 ,  G11C29/781 ,  G11C7/067

摘要： A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry. A transistor having a large channel resistance, however, is placed within a feedback path of the latch. Therefore, after the latch is set, if the antifuse cell is blown, the high resistance transistor provides a resistive current path from the V.sub.CC to ground.

公开(公告)号：US5966388A

公开(公告)日：1999-10-12

申请号：US779036

申请日：1997-01-06

申请人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

发明人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/34 ,  G11C29/38 ,  G06F11/00

CPC分类号： G11C29/38 ,  G11C29/34

摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.

摘要翻译： 存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。 来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。 用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。 压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。 比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。 测试标志通过多路复用器输出到第二个DQ线。 因此，可以从第一DQ线测试器件的速度，而可以在第二DQ线上对片上比较的结果进行采样。 比较电路不仅比较给定数据字的位，而且比较来自另一个数据字的至少一位。 因此，不是采用比较第一和第二数据字的两个比较电路，而是比较前两个比较电路的结果的第三比较电路，本发明通过比较第一和第二数据字的第一数据字， 具有来自第二数据字的至少一位的第一比较电路。

公开(公告)号：US5895962A

公开(公告)日：1999-04-20

申请号：US664109

申请日：1996-06-13

申请人： Hua Zheng ,  Michael Shore ,  Jeffrey P. Wright ,  Todd A. Merritt

发明人： Hua Zheng ,  Michael Shore ,  Jeffrey P. Wright ,  Todd A. Merritt

IPC分类号： G01R31/3181 ,  G11C17/10 ,  H01L27/112 ,  H01L27/04 ,  G11C17/00

CPC分类号： G01R31/3181 ,  G11C17/10 ,  H01L27/112

摘要： A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer. Each of the storage elements is formed in a predetermined state such that they collectively store a digital value that identifies a mask used to form the conductive layer.

摘要翻译： 半导体器件包括形成在衬底上的多个导电层。 共同组成存储元件的只读存储元件（例如熔丝元件）的两个电互相耦合部分分别形成在不同的一个导电层中。 存储元件具有存储状态，并且每个部分具有导电性。 可以通过改变其中一个部分的电导率来改变存储元件的存储状态。 另外，多个存储元件可以并联耦合以形成存储模块。 存储模块的每个存储元件可以包括各自形成在不同导电层中的多个存储部分。 存储元件可以存储用于形成半导体器件的掩模集的版本号。 或者，在衬底上形成导电层，并且在导电层中形成一个或多个只读存储元件。 每个存储元件形成为预定状态，使得它们共同地存储识别用于形成导电层的掩模的数字值。

公开(公告)号：US5875144A

公开(公告)日：1999-02-23

申请号：US915075

申请日：1997-08-20

申请人： Hua Zheng

发明人： Hua Zheng

IPC分类号： G11C7/06 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C29/789 ,  G11C29/781 ,  G11C7/067

摘要： A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry. A transistor having a large channel resistance, however, is placed within a feedback path of the latch. Therefore, after the latch is set, if the antifuse cell is blown, the high resistance transistor provides a resistive current path from the V.sub.CC to ground.

公开(公告)号：US5805505A

公开(公告)日：1998-09-08

申请号：US767181

申请日：1996-12-16

申请人： Hua Zheng ,  Jeffrey P. Wright

发明人： Hua Zheng ,  Jeffrey P. Wright

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K19/00 ,  H03K19/017 ,  G11C7/00 ,  H03K17/16

CPC分类号： H03K19/0013 ,  G11C7/1051 ,  G11C7/22 ,  H03K19/01707

摘要： A circuit converts first and second input signals having first and second active levels, respectively, into an output signal. The circuit includes first and second input terminals, an output terminal and first and second drive terminals. A first stage of the circuit is coupled to the first input terminal, the first drive terminal and the output terminal. The first stage couples a first impedance between the first drive terminal and the output terminal when the first input signal is at the first active level, and reduces the magnitude of the first impedance for a first predetermined time after the first input signal transitions to the first active level. A second stage is coupled to the second input terminal, the second drive terminal and the output terminal, and couples a second impedance between the second drive terminal and the output terminal when the second input signal is at the second active level. The second stage may reduce the magnitude of the second impedance for a second predetermined time after the second input signal transitions to the second active level.

摘要翻译： 电路将具有第一和第二有效电平的第一和第二输入信号分别转换成输出信号。 该电路包括第一和第二输入端子，输出端子和第一和第二驱动端子。 电路的第一级耦合到第一输入端子，第一驱动端子和输出端子。 当第一输入信号处于第一有效电平时，第一级耦合第一驱动端和输出端之间的第一阻抗，并且在第一输入信号转变到第一输入信号之后的第一预定时间内减小第一阻抗的幅值 活跃水平 第二级耦合到第二输入端子，第二驱动端子和输出端子，并且当第二输入信号处于第二有效电平时，在第二驱动端子和输出端子之间耦合第二阻抗。 第二级可以在第二输入信号转换到第二有效电平之后的第二预定时间内减小第二阻抗的幅度。

公开(公告)号：US5796266A

公开(公告)日：1998-08-18

申请号：US619261

申请日：1996-03-18

申请人： Jeffrey P. Wright ,  Hua Zheng

发明人： Jeffrey P. Wright ,  Hua Zheng

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G01R31/02

CPC分类号： G01R31/2648 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905

摘要： An integrated device includes a configuration circuit that is coupled to first and second bond pads and first and second conductive paths of the integrated device. The circuit receives a map signal that has a first value during a first operational mode of the integrated device and a second value during a second operational mode of the integrated device. In response to the first value, the circuit couples the first pad to the second conductive path. In response to the second value, the circuit couples the first pad to the first conductive path and the second pad to the second conductive path. The first operational mode may be a wafer test mode.