利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

99 条记录 (耗时 0.044 秒)

    High-speed test system for a memory device
    1.
    发明授权
    High-speed test system for a memory device 有权
    高速测试系统用于存储器件

    公开(公告)号：US06154860A

    公开(公告)日：2000-11-28

    申请号：US321295

    申请日：1999-05-27

    申请人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    发明人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/34 ,  G11C29/38

    CPC分类号： G11C29/38 ,  G11C29/34

    摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.

    摘要翻译： 存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。 来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。 用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。 压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。 比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。 测试标志通过多路复用器输出到第二个DQ线。 因此，可以从第一DQ线测试器件的速度，而可以在第二DQ线上对片上比较的结果进行采样。

    High speed test system for a memory device
    2.
    发明授权
    High speed test system for a memory device 有权
    高速测试系统用于存储器件

    公开(公告)号：US06550026B1

    公开(公告)日：2003-04-15

    申请号：US09724346

    申请日：2000-11-27

    申请人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    发明人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    IPC分类号： G11C2900

    CPC分类号： G11C29/38 ,  G11C29/34

    摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.

    摘要翻译： 存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。 来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。 用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。 压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。 比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。 测试标志通过多路复用器输出到第二个DQ线。 因此，可以从第一个DQ线路测试器件的速度，而可以在第二个DQ线路上对片上比较的结果进行采样。比较电路不仅比较给定数据字的位，还可以比较给定数据字的位 来自另一数据字的至少一位。 因此，不是采用比较第一和第二数据字的两个比较电路，而是比较前两个比较电路的结果的第三比较电路，本发明通过比较第一和第二数据字的第一数据字， 具有来自第二数据字的至少一位的第一比较电路。

    High-speed test system for a memory device
    3.
    发明授权
    High-speed test system for a memory device 失效
    高速测试系统用于存储器件

    公开(公告)号：US5966388A

    公开(公告)日：1999-10-12

    申请号：US779036

    申请日：1997-01-06

    申请人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    发明人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/34 ,  G11C29/38 ,  G06F11/00

    CPC分类号： G11C29/38 ,  G11C29/34

    摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.

    摘要翻译： 存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。 来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。 用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。 压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。 比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。 测试标志通过多路复用器输出到第二个DQ线。 因此，可以从第一DQ线测试器件的速度，而可以在第二DQ线上对片上比较的结果进行采样。 比较电路不仅比较给定数据字的位，而且比较来自另一个数据字的至少一位。 因此，不是采用比较第一和第二数据字的两个比较电路，而是比较前两个比较电路的结果的第三比较电路，本发明通过比较第一和第二数据字的第一数据字， 具有来自第二数据字的至少一位的第一比较电路。

    Synchronous dynamic random access memory device
    4.
    发明授权
    Synchronous dynamic random access memory device 有权

    公开(公告)号：US06512711B1

    公开(公告)日：2003-01-28

    申请号：US09572820

    申请日：2000-05-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

    摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

    Synchronous dynamic random access memory device
    6.
    发明授权
    Synchronous dynamic random access memory device 有权

    公开(公告)号：US06351404B1

    公开(公告)日：2002-02-26

    申请号：US09572387

    申请日：2000-05-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C502

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

    摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

    Circuit and method for providing a substantially constant time delay over a range of supply voltages
    8.
    发明授权
    Circuit and method for providing a substantially constant time delay over a range of supply voltages 有权
    电路和方法，用于在电源电压范围内提供基本恒定的时间延迟

    公开(公告)号：US6044027A

    公开(公告)日：2000-03-28

    申请号：US333818

    申请日：1999-06-15

    申请人： Hua Zheng ,  Jeffrey P. Wright

    发明人： Hua Zheng ,  Jeffrey P. Wright

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  H03K5/13 ,  H03K5/135 ,  G11C5/14

    CPC分类号： H03K5/133 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  H03K5/135

    摘要： A delay circuit provides a substantially constant delay over a range of power-supply voltages. The delay circuit includes an input terminal that receives an input signal, an output terminal that provides an output signal, and a supply terminal that receives a supply voltage. A delay stage is coupled between the input and the output terminals and, when the supply voltage has a predetermined value, generates the output signal a predetermined delay time after it receives the input signal. A control stage is coupled between the supply terminal and the delay stage and regulates the supply current that flows between the supply terminal and the delay stage such that the delay time of the delay stage remains substantially equal to the predetermined delay time as the supply voltage varies from the predetermined value.

    摘要翻译： 延迟电路在一定范围的电源电压上提供基本恒定的延迟。 延迟电路包括接收输入信号的输入端子，提供输出信号的输出端子和接收电源电压的电源端子。 延迟级耦合在输入端子和输出端子之间，并且当电源电压具有预定值时，在输入信号接收到输入信号之后产生预定的延迟时间。 控制级耦合在电源端子和延迟级之间，并且调节在电源端子和延迟级之间流动的电源电流，使得延迟级的延迟时间保持基本上等于预定延迟时间，因为电源电压变化 从预定值。

    Clock frequency detector for a synchronous memory device
    9.
    发明授权
    Clock frequency detector for a synchronous memory device 失效

    公开(公告)号：US5784332A

    公开(公告)日：1998-07-21

    申请号：US764488

    申请日：1996-12-12

    申请人： Hua Zheng ,  Jeffrey P. Wright

    发明人： Hua Zheng ,  Jeffrey P. Wright

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00

    CPC分类号： G11C7/225 ,  G11C7/1072 ,  G11C7/22

    摘要： The present invention employs a clock frequency detector in a SDRAM that detects whether an input clock signal is operating at a fast rate (e.g., 125 MHz or a 8 nanosecond access time), or at a slower rate. In response to the input clock frequency, the clock frequency detector outputs a selection signal to control logic circuitry in the SDRAM indicating whether the SDRAM should operate in either a fast or slow mode. The clock frequency detector employs a frequency detector that detects the frequency of the input clock signal. Based on the frequency of the input clock signal, a selector circuit outputs either a fast or slow selection signal to the control logic circuitry. In response to the fast selection signal, the control logic circuitry performs data access commands at a fast rate, while in response to the slow selection signal, the control logic circuitry executes such commands at a slower, more conservative rate. As a result, the SDRAM device can operate according to its maximum specifications in connection with a fast input clock rate (allowing essentially no margins for error), or perform at a slower rate based on a slower input clock frequency (allowing for some margin of error).