-
91.发明授权公开(公告)号：US06351787B2
公开(公告)日：2002-02-26
申请号：US09793967
申请日：2001-02-28
IPC分类号： G06F1200
CPC分类号： G06F3/0613 , G06F3/0601 , G06F3/064 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F12/023 , G06F12/0246 , G06F2003/0694 , G06F2212/7208
摘要： A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance. The file memory device includes a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device, and a data access width smaller than the data bus; a file division unit for dividing file data having one or more unit storage data blocks into combined blocks that include a combination of arbitrary unit storage data blocks; a data distribution unit for arbitrarily combining data on the data bus having a unit data size equal to the data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control unit for controlling the data distribution unit so that each combined block is stored in the file memory device based on a correspondence between the combined block and arbitrary combinations of memory elements.
摘要翻译： 半导体文件存储装置以及包含该装置的信息处理系统使用闪速存储器来实现快速的文件访问性能。 所述文件存储装置包括具有大于所述存储装置的数据总线宽度的单位擦除块大小的存储元件组的并行布置以及小于所述数据总线的数据访问宽度; 文件分割单元，用于将具有一个或多个单元存储数据块的文件数据分成包括任意单位存储数据块的组合的组合块; 数据分配单元，用于任意组合数据总线上具有与数据访问宽度相等的单位数据大小的数据，并且用于使组合数据对应于与单位大小数据相等的存储单元组的任意组合; 以及控制单元，用于基于组合块和存储元件的任意组合之间的对应关系来控制数据分配单元，使得每个组合块被存储在文件存储设备中。
-
92.发明授权Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory 有权具有错误校正单元的存储设备和用于访问和传送存储在非易失性半导体存储器中的数据块的改进布置公开(公告)号：US06317371B2
公开(公告)日：2001-11-13
申请号：US09824778
申请日：2001-04-04
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C700
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。
-
公开(公告)号：US06236601B1
公开(公告)日：2001-05-22
申请号：US09477665
申请日：2000-01-05
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C700
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.
摘要翻译： 一种具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。 如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。 此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。
-
94.发明授权Test device employing scan path having circuitry at switches between a scan in signal transmitted and previously held at a predetermined clock timing 失效使用扫描路径的测试装置，其具有在以预定时钟定时发送的信号和先前保持的信号中的切换开关之间的电路
公开(公告)号：US5848075A
公开(公告)日：1998-12-08
申请号：US772850
申请日：1996-12-24
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318541
摘要： A test device which employs a scan path method includes a latch circuit for holding a scan in signal, a transfer gate connected between the scan in signal and an input terminal of the latch circuit and having a gate terminal receiving a clock signal, a select circuit for selecting one of a data signal and an output signal from the latch circuit in response to a mode select signal and for outputting the selected signal, and a flipflop circuit for holding an output signal from the select circuit in response to the clock signal and for outputting the held signal as a scan out signal.
摘要翻译： 采用扫描路径法的测试装置包括用于保持扫描信号的锁存电路，连接在扫描信号与锁存电路的输入端之间并具有接收时钟信号的栅极端子的传输门，选择电路 用于响应于模式选择信号选择来自锁存电路的数据信号和输出信号之一并输出所选择的信号;以及触发电路，用于响应于时钟信号保持来自选择电路的输出信号，并且用于 输出保持的信号作为扫描输出信号。
-
公开(公告)号：US20110034124A1
公开(公告)日：2011-02-10
申请号：US12838467
申请日：2010-07-18
IPC分类号： H04B5/00
CPC分类号： H04B5/0056 , G06K7/0008 , G06K7/10207
摘要： A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.
摘要翻译： 提供了即使在从电池电力下降操作电压之后，也可以连续使用通过非接触式通信的认证和结算功能的移动通信终端设备。 只有当电池所需电力的供给丢失时，才能将安全控制器控制为低功耗运行的模式，并通过外部电磁场功率确保非接触式认证和结算功能。 因此，即使在通过使用用于主要目的的通信功能的电池剩余容量丢失之后，也可以使用非接触式认证和结算功能。 具体而言，实现以下方式：当从电池供给所需电力时，可以进行高性能，多功能的认证和结算处理，从而充分利用高速处理，大容量存储等 这是安全控制器基本上由电池驱动的优点; 并且在电池剩余容量损失的异常情况下，可以进行最小的认证和结算处理。
-
96.发明授权Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权具有电可擦除和可编程的半导体存储器单元的半导体存储器公开(公告)号：US07881111B2
公开(公告)日：2011-02-01
申请号：US12504307
申请日：2009-07-16
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
摘要翻译： 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。
-
公开(公告)号：US07721165B2
公开(公告)日：2010-05-18
申请号：US11599388
申请日：2006-11-15
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译： 一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统， 对连续扇区数据的读命令作出响应。
-
公开(公告)号：US07549086B2
公开(公告)日：2009-06-16
申请号：US11877500
申请日：2007-10-23
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
-
公开(公告)号：US20080301817A1
公开(公告)日：2008-12-04
申请号：US12182123
申请日：2008-07-29
IPC分类号： G06F21/00
CPC分类号： G06F21/78 , G06F21/31 , G06F2221/2143
摘要： In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.
摘要翻译： 为了保护用户安全数据，提供了一种能够通过对密码认证数量进行限制并自动擦除数据来防止数据泄漏给不具有访问权限的第三方的存储卡。 在由多媒体卡和与多媒体卡电连接并控制多媒体卡的操作的主机构成的系统中，提供用于存储密码认证失败次数的重试计数器，故障次数的上限为 注册登记。 当密码重复输入一次，两次，。 。 。 并且n次，对条目进行计数的重试计数器达到故障次数的上限，数据被自动擦除，以便不将数据留在闪存中。
-
公开(公告)号：US07343445B2
公开(公告)日：2008-03-11
申请号：US11541543
申请日：2006-10-03
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译： 存储卡设置有传送控制电路，写入控制电路和判断电路。 传送控制电路在数据传送期间输出传送标志信号。 写入控制电路在数据写入操作期间输出内部忙信号。 当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。 因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。
-
-
-
-
-
-
-
-
-
搜索结果
146 条记录 (耗时 0.041 秒)
