公开(公告)号：US06180698B2

公开(公告)日：2001-01-30

申请号：US08808363

申请日：1997-02-28

申请人： John D. Porter ,  Scott J. Crane ,  Stephanie J. Oberg ,  Anthony W. Johnson

发明人： John D. Porter ,  Scott J. Crane ,  Stephanie J. Oberg ,  Anthony W. Johnson

IPC分类号： C08K534

CPC分类号： C08J3/096 ,  C08J3/09 ,  C08J5/18 ,  C08J2369/00 ,  H01J9/025 ,  H01J2329/00

摘要： A liquid chemical formulation suitable for making a thin solid polycarbonate film of highly uniform thickness is formed with polycarbonate material, a liquid that dissolves the polycarbonate, and possibly one or more other constituents. The liquid is typically capable of dissolving the polycarbonate to a concentration of at least 1% at 20° C. and 1 atmosphere. The liquid also typically has a boiling point of at least 80° C. at 1 atmosphere. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derivative, and cyclohexanone. In forming the polycarbonate-containing film, a liquid film (36A) of the liquid chemical formulation is formed over a substructure (30). The liquid film is processed to largely remove the liquid and convert the polycarbonate into a solid film (38).

摘要翻译： 用聚碳酸酯材料，可溶解聚碳酸酯的液体以及可能的一种或多种其它组分形成适于制备厚度均匀的薄的固体聚碳酸酯薄膜的液体化学制剂。 该液体通常能够在20℃和1个大气压下将聚碳酸酯溶解至少1％的浓度。 该液体通常在1个大气压下的沸点至少为80℃。 液体的实例包括吡啶，环取代的吡啶衍生物，吡咯，环取代的吡咯衍生物，吡咯烷，吡咯烷衍生物和环己酮。 在形成含聚碳酸酯的膜中，在子结构（30）上形成液体化学制剂的液膜（36A）。 处理液膜以大量去除液体并将聚碳酸酯转化成固体膜（38）。

公开(公告)号：US6040713A

公开(公告)日：2000-03-21

申请号：US64531

申请日：1998-04-22

申请人： John D. Porter ,  Larren G. Weber ,  William N. Thompson

发明人： John D. Porter ,  Larren G. Weber ,  William N. Thompson

IPC分类号： H03K5/02 ,  H03K5/12 ,  H03K5/1252 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K5/023 ,  H03K5/12 ,  H03K5/1252

摘要： A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

摘要翻译： 具有第一和第二输入端子和输出端子的缓冲器。 缓冲器还包括具有输入端和输出端的快速边沿驱动器，输入端连接到缓冲器的第一输入端，输出端连接到缓冲器的输出端。 提供具有输入端子和输出端子的屏蔽电路，输入端子连接到缓冲器的第二输入端子。 该缓冲器还包括具有输入端和输出端的恢复电路，输入端连接到屏蔽电路的输出端，输出端连接到缓冲器的输出端。

公开(公告)号：US6004180A

公开(公告)日：1999-12-21

申请号：US940873

申请日：1997-09-30

申请人： N. Johan Knall ,  John D. Porter ,  Colin D. Stanners ,  Christopher J. Spindt ,  Victoria A. Bascom

发明人： N. Johan Knall ,  John D. Porter ,  Colin D. Stanners ,  Christopher J. Spindt ,  Victoria A. Bascom

IPC分类号： H01J9/38 ,  H01J9/02

CPC分类号： H01J9/025

摘要： Multiple procedures are presented for removing contaminant material (12) from electron-emissive elements (10) of an electron-emitting device (30). One procedure involves converting the contaminant material into gaseous products (14), typically by operating the electron-emissive elements, that move away from the electron-emissive elements. Another procedure entails converting the contaminant material into further material (16) and removing the further material. An additional procedure involves forming surface coatings (18 or 20) over the electron-emissive elements. The contaminant material is then removed directly from the surface coatings or by removing at least part of each surface coating.

摘要翻译： 提出了用于从电子发射器件（30）的电子发射元件（10）去除污染物质（12）的多个步骤。 一种方法包括通常通过操作远离电子发射元件的电子发射元件将污染物质转化为气体产物（14）。 另一个过程需要将污染物质转化成另外的材料（16）并除去其它材料。 另外的过程涉及在电子发射元件上形成表面涂层（18或20）。 然后直接从表面涂层去除污染物质，或者通过去除每个表面涂层的至少一部分。

公开(公告)号：US5565794A

公开(公告)日：1996-10-15

申请号：US494271

申请日：1995-06-23

申请人： John D. Porter

发明人： John D. Porter

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/094 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/01721 ,  H03K19/00315 ,  H03K19/00384 ,  H03K19/09429

摘要： A tri-state CMOS output buffer is provided which exhibits a relatively low input capacitance and tolerance to a range of operating voltages. The output buffer includes a PUP input, a PD input and an output. The output buffer includes a source follower circuit coupled to the PUP input such that the output of the source follower generally follows transitions in the PUP input signal. The source follower output is the buffer output. A pull-down transistor is coupled between the buffer output and ground to pull-down the output voltage when the PD signal goes high. A pull-up transistor and an isolation transistor are coupled in series to form a series coupled circuit. This series-coupled circuit is coupled in parallel with the source follower. The pull-up transistor pulls up the voltage on the buffer output when the PUP input signal goes high. The isolation transistor is switchable to an off state to isolate a parasitic diode associated with the pull-up transistor. A control circuit is coupled to the buffer output and the PUP input to monitor the buffer output and the PUP input to turn off the isolation transistor when the buffer output is in a tri-state condition and the buffer output is driven high by an external device. Otherwise, the control circuit causes the isolation transistor to remain on. In this manner, isolation transistor switching is significantly reduced and the capacitive load presented to the PUP input signal is substantially lowered.

摘要翻译： 提供三态CMOS输出缓冲器，其表现出相对低的输入电容和对一定范围的工作电压的容限。 输出缓冲器包括PUP输入，PD输入和输出。 输出缓冲器包括耦合到PUP输入的源极跟随器电路，使得源极跟随器的输出通常遵循PUP输入信号中的跃迁。 源跟随器输出是缓冲器输出。 当PD信号变为高电平时，下拉晶体管耦合在缓冲器输出和地之间以降低输出电压。 上拉晶体管和隔离晶体管串联耦合以形成串联耦合电路。 该串联电路与源极跟随器并联耦合。 当PUP输入信号变为高电平时，上拉晶体管拉高缓冲器输出上的电压。 隔离晶体管可切换到截止状态以隔离与上拉晶体管相关联的寄生二极管。 当缓冲器输出处于三态条件时，控制电路耦合到缓冲器输出和PUP输入以监视缓冲器输出和PUP输入以关闭隔离晶体管，并且缓冲器输出由外部设备驱动为高电平 。 否则，控制电路使隔离晶体管保持导通。 以这种方式，隔离晶体管开关显着降低，并且呈现给PUP输入信号的电容性负载显着降低。

公开(公告)号：US5268866A

公开(公告)日：1993-12-07

申请号：US844022

申请日：1992-03-02

申请人： Tiasheng Feng ,  Stephen T. Flannagan ,  John D. Porter

发明人： Tiasheng Feng ,  Stephen T. Flannagan ,  John D. Porter

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/846 ,  G11C29/78

摘要： A memory (20) has a plurality of columns of memory cells and has a plurality of redundant columns of memory cells. A comparator (45) detects an access to a defective column. A redundant write generator (31) and write fuses (32) are provided for each write portion (30A, 30B, 30C, and 30D) to replace the defective column with a redundant column by replacing a write global data line (37) with a redundant write global data line (39). Redundant read generators (60 and 61) and read fuses (59) are provided for each read portion (50A, 50B, 50C, and 50D) to replace a defective column by deselecting a read global data line (29) and replacing it with a redundant read global data line (44). The fuses and redundant generators are located close to their global data lines, thus reducing the routing of control signals and improving the access time of redundant columns.

公开(公告)号：US08743640B2

公开(公告)日：2014-06-03

申请号：US13752037

申请日：2013-01-28

申请人： Jennifer Taylor ,  John D. Porter

发明人： Jennifer Taylor ,  John D. Porter

IPC分类号： G11C7/02

CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C27/005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2213/72 ,  G11C2213/79

摘要： Methods and systems for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

摘要翻译： 公开了用于测量多个存储元件的电阻的方法和系统。 存储器元件可以是多位存储器，并且通过精确测量多位存储器元件的电阻，可以实现多少和哪些存储器元件落入特定存储器范围的确定。 此外，该信息的存储和/或显示可以允许创建用于一个或多个存储器阵列的建模的电阻分布直方图。

公开(公告)号：US08649207B2

公开(公告)日：2014-02-11

申请号：US13619253

申请日：2012-09-14

申请人： Pradeep Ramani ,  John D. Porter

发明人： Pradeep Ramani ,  John D. Porter

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2213/31 ,  G11C2213/32

摘要： The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.

摘要翻译： 本公开包括用于操作电阻变量存储器的装置和方法。 一个设备实施例包括一组存储器单元，其中多个单元共同耦合到选择线，所述数量单元包括在多个目标阈值电阻（Rt）范围内可编程的多个数据单元，其数量对应于 数据状态，以及与数据单元交错并且在目标Rt范围的数目内可编程的多个参考单元。 上述设备实施例还包括耦合到阵列并被配置为感测与至少一个数据单元和至少一个参考单元相关联的电平的控制电路，并且将感测到的与至少一个数据单元相关联的电平与感测电平相关联 与所述至少一个参考单元确定所述至少一个数据单元的数据状态。

公开(公告)号：US08559218B2

公开(公告)日：2013-10-15

申请号：US13101307

申请日：2011-05-05

申请人： John D. Porter ,  Jennifer E. Taylor

发明人： John D. Porter ,  Jennifer E. Taylor

IPC分类号： G11C11/00

CPC分类号： G11C17/16 ,  G11C7/04 ,  G11C7/1006 ,  G11C17/18

摘要： Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.

摘要翻译： 还包括用于存储器件中的温度补偿的装置，方法和系统，例如电阻变量存储器以及其它类型的存储器。 一个或多个实施例可以包括存储器设备，其包括具有输出的表，该输出用于产生用于补偿存储器件中的温度变化的电流的乘法因子，其中输出取决于存储器件的工作温度和 存储器件的最高规定工作温度和最低规定工作温度之间的电流差。

公开(公告)号：US08406027B2

公开(公告)日：2013-03-26

申请号：US13210709

申请日：2011-08-16

申请人： John D. Porter

发明人： John D. Porter

IPC分类号： G11C5/02 ,  G11C7/10

CPC分类号： G11C13/0011 ,  G11C5/025 ,  G11C5/14 ,  G11C7/12 ,  G11C11/5621 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/79 ,  Y10T29/49117

摘要： The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

摘要翻译： 本公开包括用于编程存储器的装置，方法和系统，例如电阻变量存储器。 一个实施例可以包括电阻可变存储单元的阵列，其中电阻可变存储单元耦合到一个或多个数据线，连接到阵列的第一侧的行解码器，连接到阵列第二侧的列解码器 ，其中所述第二侧与所述第一侧相邻，位于所述行解码器和所述列解码器附近的间隙以及被配置为在编程操作期间控制与一个或多个未选择的存储器单元相关联的反向偏置电压的钳位电路，其中， 钳位电路位于间隙中，并且选择性地耦合到一个或多个数据线。

公开(公告)号：US08363500B2

公开(公告)日：2013-01-29

申请号：US13159288

申请日：2011-06-13

申请人： Jennifer Taylor ,  John D. Porter

发明人： Jennifer Taylor ,  John D. Porter

IPC分类号： G11C7/02

CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C27/005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2213/72 ,  G11C2213/79

摘要： Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

摘要翻译： 公开了用于测量多个存储元件的电阻的方法。 存储器元件可以是多位存储器，并且通过精确测量多位存储器元件的电阻，可以实现多少和哪些存储器元件落入特定存储器范围的确定。 此外，该信息的存储和/或显示可以允许创建用于一个或多个存储器阵列的建模的电阻分布直方图。