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    Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon
    93.
    发明授权
    Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon 有权
    半导体形貌包括集成了多层多晶硅层的集成电路栅极导体

    公开(公告)号：US6137145A

    公开(公告)日：2000-10-24

    申请号：US237773

    申请日：1999-01-26

    申请人： Jon D. Cheek ,  Daniel Kadosh ,  Mark W. Michael

    发明人： Jon D. Cheek ,  Daniel Kadosh ,  Mark W. Michael

    IPC分类号： H01L21/8234 ,  H01K29/76

    CPC分类号： H01L21/82345

    摘要： A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal. The first gate conductor may be doped with a first dopant that has a lower diffusion rate through polysilicon than a second dopant with which the second gate conductor is doped. The second polysilicon layer portion of the second gate conductor is substantially free of implanted dopants.

    摘要翻译： 提供包括并入双多晶硅层的集成电路栅极导体的半导体形貌。 半导体形貌包括半导体衬底。 第一栅极导体布置在第一栅极电介质上并位于半导体衬底之上，并且第二栅极导体布置在第二栅极电介质上并位于半导体衬底之上。 半导体衬底可以包含通过场区域与第二有源区域横向分离的第一有源区域。 第一栅极导体可以布置在第一有源区内，并且第二栅极导体可以布置在第二有源区内。 每个栅极导体优选地包括布置在第一多晶硅层部分上的第二多晶硅层部分。 第一栅极导体和第二栅极导体的厚度优选相等。 第一栅极导体可以掺杂有第一掺杂剂，其通过多晶硅具有比掺杂第二栅极导体的第二掺杂物更低的扩散速率。 第二栅极导体的第二多晶硅层部分基本上没有注入的掺杂剂。

    Method of forming a local interconnect by conductive layer patterning
    94.
    发明授权
    Method of forming a local interconnect by conductive layer patterning 失效
    通过导电层图案形成局部互连的方法

    公开(公告)号：US6096639A

    公开(公告)日：2000-08-01

    申请号：US056835

    申请日：1998-04-07

    申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76895

    摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

    摘要翻译： 通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。 在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。 在一些实施例中，钛是用于形成局部互连的合适金属。 用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。 硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。 在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。 在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。

    Fabrication of a non-ldd graded p-channel mosfet
    95.
    发明授权
    Fabrication of a non-ldd graded p-channel mosfet 失效
    制造非ldd分级p沟道mosfet

    公开(公告)号：US6096616A

    公开(公告)日：2000-08-01

    申请号：US80658

    申请日：1998-05-18

    申请人： John L. Nistler ,  Mark W. Michael

    发明人： John L. Nistler ,  Mark W. Michael

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L29/7833 ,  H01L29/665

    摘要： A transistor and transistor fabrication method are presented in which a graded junction is formed using a plurality of source/drain dopant implants. The implants are performed such that higher concentrations of dopant species are implanted at lower energies and lower dopant concentrations are implanted at higher energies. In an embodiment, an anneal step is used to create the graded junction by exploiting the concentration dependence of the dopant diffusivity (i.e., dopant species implanted in regions of high concentration are more mobile than dopant species implanted in regions of low concentration). Sub-0.25-micron transistors formed by the process described herein may be less susceptible to deleterious capacitive loading and parasitic resistance than transistors having conventionally formed lightly doped drain and source/drain implants. Transistors formed according to the method of this application may also advantageously include highly doped shallow junctions while incorporating lightly doped deeper junctions to avoid the problem of junction spiking. Integrated circuits including transistors formed according to the method described herein may further be subject to less inter-transistor variation in effective channel length, and therefore threshold voltage roll-off and drive current variability, than integrated circuits including conventionally formed transistors.

    摘要翻译： 提出了一种晶体管和晶体管制造方法，其中使用多个源极/漏极掺杂剂种植体形成渐变结。 进行这样的种植体，使得较高浓度的掺杂剂种类以较低的能量注入，较低的掺杂剂浓度以更高的能量注入。 在一个实施例中，使用退火步骤通过利用掺杂剂扩散率的浓度依赖性（即，注入在高浓度区域中的掺杂剂物质比注入低浓度区域的掺杂剂物质更可移动）来产生分级结。 通过本文所述的方法形成的次级0.25微米晶体管可能比具有常规形成的轻掺杂漏极和源极/漏极注入的晶体管更不易受有害电容负载和寄生电阻的影响。 根据本申请的方法形成的晶体管还可以有利地包括高度掺杂的浅结，同时结合轻掺杂的较深的结，以避免接合尖峰的问题。 包括根据本文描述的方法形成的晶体管的集成电路可以进一步与包括常规形成的晶体管的集成电路相比，在有效沟道长度，因此阈值电压滚降和驱动电流变化性方面进行更少的晶体管间变化。

    Dissolvable dielectric method and structure
    96.
    发明授权
    Dissolvable dielectric method and structure 有权
    溶解介电法和结构

    公开(公告)号：US6091149A

    公开(公告)日：2000-07-18

    申请号：US251059

    申请日：1999-02-18

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/7682

    摘要： A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.

    摘要翻译： 提供一种制造工艺，其产生气隙电介质，其中在临时支撑材料上形成多层互连结构。 随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。 在本发明的一个实施例中，在阻挡层上形成第一互连电平。 然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。 在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。 除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。 临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。 在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。 如果需要，气隙电介质可以与多于两个级别的互连一起使用。

    Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization
    98.
    发明授权
    Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
    用于制造具有最佳金属互连布局以实现全局平坦化的集成电路的掩模生成技术

    公开(公告)号：US6049134A

    公开(公告)日：2000-04-11

    申请号：US15821

    申请日：1998-01-29

    申请人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

    发明人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

    IPC分类号： H01L21/033 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/72 ,  H01L21/283

    CPC分类号： H01L21/0334 ,  H01L21/31051 ,  H01L21/76819

    摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

    摘要翻译： 提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。 衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化 抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

    Semiconductor substrate having extended scribe line test structure and method of fabrication thereof
    99.
    发明授权
    Semiconductor substrate having extended scribe line test structure and method of fabrication thereof 失效
    具有延长的划片线测试结构的半导体衬底及其制造方法

    公开(公告)号：US6027859A

    公开(公告)日：2000-02-22

    申请号：US992234

    申请日：1997-12-17

    申请人： Robert Dawson ,  Mark W. Michael ,  Fred Hause

    发明人： Robert Dawson ,  Mark W. Michael ,  Fred Hause

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70633 ,  G03F7/70475

    摘要： The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes forming a first test structure pattern over a first portion of the substrate and forming a second test structure pattern of the second portion of the substrate which partially overlaps the first portion of the substrate such that the first test structure pattern and the second test structure overlap. The first test structure pattern may be formed using, for example, reticle and a second test structure pattern may be formed using the same reticle. The first and second test structure patterns may, for example, be formed in a scribe line of the substrate.

    摘要翻译： 本发明通常提供具有扩展测试结构的半导体衬底和制造这种衬底的方法。 根据本发明的一个实施例，在半导体衬底上形成扩展测试结构的方法包括在衬底的第一部分上形成第一测试结构图案，并形成衬底的第二部分的第二测试结构图案， 部分地与衬底的第一部分重叠，使得第一测试结构图案和第二测试结构重叠。 可以使用例如掩模版形成第一测试结构图案，并且可以使用相同的掩模版形成第二测试结构图案。 第一和第二测试结构图案可以例如形成在基板的划线中。

    Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
    100.
    发明授权
    Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
    具有气隙的集成电路的多层互连结构和分离互连级别的柱

    公开(公告)号：US5998293A

    公开(公告)日：1999-12-07

    申请号：US67425

    申请日：1998-04-28

    申请人： Robert Dawson ,  Mark W. Michael ,  William S. Brennan ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause

    发明人： Robert Dawson ,  Mark W. Michael ,  William S. Brennan ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/283

    CPC分类号： H01L23/5226 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5222 ,  H01L2924/0002

    摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

    摘要翻译： 提供了一种改进的多级互连结构。 互连结构包括跨越晶片彼此间隔开的柱。 支柱放置在互连层之间或互连层和半导体衬底之间。 支柱通过空气间隙彼此分开，使得互连级别内的每个导体彼此间隔着空气。 此外，一个级别的互连中的每个导体在另一个互连级别内的每个导体间隔着空气。 空气间隙在多电平互连结构内提供较小的层间和体积电容，并且较小的寄生电容值提供通过导体发送的信号的最小传播延迟和交叉耦合噪声。 通过溶解牺牲电介质形成气隙，并且通过不仅在每个导体的上表面，而且侧壁上采用阳极氧化，防止导体在去除牺牲电介质的区域中弯曲或翘曲。 上侧壁和侧壁阳极氧化提供了比仅仅将上表面或侧壁表面阳极氧化的更刚性的金属导体结构。 因此，支柱可以进一步间隔开，并且向上覆的导体提供所有必要的支撑。