利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

116 条记录 (耗时 0.04 秒)

    Semiconductor integrated circuit device
    91.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07420834B2

    公开(公告)日：2008-09-02

    申请号：US11504077

    申请日：2006-08-15

    申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

    摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

    摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

    Semiconductor memory device and semiconductor integrated circuit device
    92.
    发明授权
    Semiconductor memory device and semiconductor integrated circuit device 有权
    半导体存储器件和半导体集成电路器件

    公开(公告)号：US07251182B2

    公开(公告)日：2007-07-31

    申请号：US11353967

    申请日：2006-02-15

    申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

    发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

    IPC分类号： G11C5/14

    CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

    摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

    摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。

    Semiconductor integrated circuit
    93.
    发明申请
    Semiconductor integrated circuit 有权

    公开(公告)号：US20070115748A1

    公开(公告)日：2007-05-24

    申请号：US11655057

    申请日：2007-01-19

    申请人： Masanori Isoda ,  Masanao Yamaoka

    发明人： Masanori Isoda ,  Masanao Yamaoka

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C11/412

    摘要： Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires. The voltage control circuit can execute control in such a manner as to reduce the potential difference of a pair of power source nodes of the static memory cell in response to indication of the low power consumption mode by the mode control circuit and can execute control in such a manner as to increase the potential difference of the pair of power source nodes of the static memory cell in response to detection of the decrease of the potential difference between the pair of power source wires by the monitor circuit.

    Semiconductor memory device
    94.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20070076467A1

    公开(公告)日：2007-04-05

    申请号：US11541542

    申请日：2006-10-03

    申请人： Masanao Yamaoka ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Takayuki Kawahara

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

    摘要翻译： 本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性 以及从漏极流到基板电极的漏电流。 本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。 本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

    Semiconductor device
    98.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08493775B2

    公开(公告)日：2013-07-23

    申请号：US13587900

    申请日：2012-08-16

    申请人： Masanao Yamaoka ,  Kenichi Osada

    发明人： Masanao Yamaoka ,  Kenichi Osada

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C11/412

    摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

    摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

    Semiconductor device and information processing apparatus using the same
    99.
    发明授权
    Semiconductor device and information processing apparatus using the same 有权
    半导体装置及使用其的信息处理装置

    公开(公告)号：US08350409B2

    公开(公告)日：2013-01-08

    申请号：US12759520

    申请日：2010-04-13

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Yasuhiro Fujimura ,  Tetsuya Fukuoka ,  Ryo Nishino

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Yasuhiro Fujimura ,  Tetsuya Fukuoka ,  Ryo Nishino

    IPC分类号： H02J1/10

    CPC分类号： G06F1/32 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/50

    摘要： Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires.In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.

    摘要翻译： 本发明的目的是通过向LSI芯片提供多个电压使得其电路块接收必要的电压并防止LSI芯片的芯片面积的增加来保持LSI芯片所需的信息处理能力，从而最小化功耗，并且 通过减少电源线的数量，可能由多个电压的供给引起的信号线的性能下降。 在提供两个电压的LSI芯片中，高压电线与低压电线相比密度更高。 通过基于电路块性能选择性地施加电压，可以在保持由LSI芯片处理的信息量的同时降低功耗。

    Semiconductor memory device
    100.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08203868B2

    公开(公告)日：2012-06-19

    申请号：US13021556

    申请日：2011-02-04

    申请人： Masanao Yamaoka ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Takayuki Kawahara

    IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06

    CPC分类号： G11C11/412

    摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

    摘要翻译： 本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性 以及从漏极流到基板电极的漏电流。 本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。 本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。