公开(公告)号：US20110024287A1

公开(公告)日：2011-02-03

申请号：US12511193

申请日：2009-07-29

Applicant: Liping Zheng ,  Hai Yang ,  Wei Cai ,  Jianyun Liu ,  Zhigang Deng ,  Hui Liu ,  Lin Chen ,  Xianguo Yu

Inventor： Liping Zheng ,  Hai Yang ,  Wei Cai ,  Jianyun Liu ,  Zhigang Deng ,  Hui Liu ,  Lin Chen ,  Xianguo Yu

IPC: C02F1/00 ,  B29C65/00

CPC classification number: C02F1/46109 ,  C02F2001/46128 ,  C02F2001/46138 ,  C02F2001/46161 ,  C02F2103/08 ,  C02F2201/46115 ,  H01G11/26 ,  H01G11/32 ,  H01G11/38 ,  H01G11/48 ,  Y02E60/13 ,  Y10T156/10

Abstract: A bipolar electrode comprises an intermediate layer comprising one or more carbon materials. The bipolar electrode further comprises first and second layers disposed on opposite surfaces of the intermediate layer and configured to act as an anode and a cathode. The first and second layers comprise at least one of one or more electrically conductive carbon materials and one or more conductive polymers. A supercapacitor desalination device and a method for making the bipolar electrode are also presented.

Abstract translation: 双极电极包括包含一种或多种碳材料的中间层。 双极电极还包括设置在中间层的相对表面上并被配置为充当阳极和阴极的第一和第二层。 第一层和第二层包括一种或多种导电碳材料和一种或多种导电聚合物中的至少一种。 还提出了超级电容器脱盐装置和制造双极性电极的方法。

公开(公告)号：US20100325486A1

公开(公告)日：2010-12-23

申请号：US12871702

申请日：2010-08-30

Applicant: Changming LIU ,  Xiaosong Yang ,  Lin Chen

Inventor： Changming LIU ,  Xiaosong Yang ,  Lin Chen

IPC: G06F11/07

CPC classification number: H04L45/00 ,  H04L43/0817 ,  H04L45/22 ,  H04L45/28

Abstract: A system includes a first network device and a second network device. The first network device includes a group of first logical portions and is configured to detect a problem with one of the first logical portions, and transmit a message identifying the one first logical portion. The second network device includes a group of second logical portions, where the group of second logical portions corresponds to the group of first logical portions. The second network device is configured to receive the message from the first network device, and activate the one second logical portion corresponding to the one first logical portion in response to receiving the message.

Abstract translation: 系统包括第一网络设备和第二网络设备。 第一网络设备包括一组第一逻辑部分，并且被配置为检测第一逻辑部分之一的问题，并且发送标识该第一逻辑部分的消息。 第二网络设备包括一组第二逻辑部分，其中第二逻辑部分组对应于第一逻辑部分的组。 第二网络设备被配置为从第一网络设备接收消息，并响应于接收到该消息而激活对应于该第一逻辑部分的一个第二逻辑部分。

公开(公告)号：US07808893B1

公开(公告)日：2010-10-05

申请号：US11037179

申请日：2005-01-19

Applicant: Changming Liu ,  Xiaosong Yang ,  Lin Chen

Inventor： Changming Liu ,  Xiaosong Yang ,  Lin Chen

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L43/0817 ,  H04L45/22 ,  H04L45/28

Abstract: A system includes a first network device and a second network device. The first network device includes a group of first logical portions and is configured to detect a problem with one of the first logical portions, and transmit a message identifying the one first logical portion. The second network device includes a group of second logical portions, where the group of second logical portions corresponds to the group of first logical portions. The second network device is configured to receive the message from the first network device, and activate the one second logical portion corresponding to the one first logical portion in response to receiving the message.

Abstract translation: 系统包括第一网络设备和第二网络设备。 第一网络设备包括一组第一逻辑部分，并且被配置为检测第一逻辑部分之一的问题，并且发送标识该第一逻辑部分的消息。 第二网络设备包括一组第二逻辑部分，其中第二逻辑部分组对应于第一逻辑部分的组。 第二网络设备被配置为从第一网络设备接收消息，并响应于接收到该消息而激活对应于该第一逻辑部分的一个第二逻辑部分。

公开(公告)号：US20100137561A1

公开(公告)日：2010-06-03

申请号：US12630002

申请日：2009-12-03

Applicant: Lin Chen

Inventor： Lin Chen

IPC: C07K14/435 ,  C07K7/08 ,  C07K7/06 ,  C07K5/103

CPC classification number: C07K14/64

Abstract: This application discloses processes for synthesizing human relaxin Chain B for treatment of diseases mediated by relaxin. This application in particular discloses processes of synthesizing the Chain B of human relaxin using a solid and solution phase (“hybrid”) approach. Generally, the approach includes synthesizing three different peptide intermediate fragments using solid phase chemistry. Solution phase chemistry is then used to couple the fragments.

Abstract translation: 本申请公开了用于治疗由松弛素介导的疾病的人松弛素B链的方法。 本申请特别公开了使用固相和溶液相（“混合”）方法合成人松弛素的链B的方法。 通常，该方法包括使用固相化学合成三种不同的肽中间体片段。 然后使用溶液相化学来连接片段。

公开(公告)号：US20100123985A1

公开(公告)日：2010-05-20

申请号：US12274085

申请日：2008-11-19

Applicant: Dening Wang ,  Yuan Gu ,  Lin Chen ,  Jonathan Scott Brodsky ,  Wei-Chung Wu ,  Wenliang Chen

Inventor： Dening Wang ,  Yuan Gu ,  Lin Chen ,  Jonathan Scott Brodsky ,  Wei-Chung Wu ,  Wenliang Chen

IPC: H02H9/04 ,  H03B1/00

CPC classification number: H02H9/046

Abstract: Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

Abstract translation: 本文公开了用于保护驾驶员免受静电放电的各种装置，方法和系统。 例如，一些示例性实施例提供了包括缓冲器的驱动器，连接到缓冲器的输出的泄漏路径阻塞晶体管，以及连接到泄漏路径阻挡晶体管的输出的输出驱动器。 从输出驱动器到缓冲器的电流基本上被泄漏路径阻断晶体管阻挡。

公开(公告)号：US20090292108A1

公开(公告)日：2009-11-26

申请号：US12316309

申请日：2008-12-11

Applicant: Lin Chen ,  Yeun-Kwei Han ,  Christopher R. Roberts

Inventor： Lin Chen ,  Yeun-Kwei Han ,  Christopher R. Roberts

IPC: C07K1/02 ,  C07K14/00 ,  C07K7/06

CPC classification number: C07K14/605

Abstract: The present invention relates to the preparation of insulinotropic peptides that are synthesized using a solid and solution phase (“hybrid”) approach. Generally, the approach includes synthesizing three different peptide intermediate fragments using solid phase chemistry. Solution phase chemistry is then used to add additional amino acid material to the third fragment which is then coupled to the second fragment and then the first fragment in solution. Alternatively, a different second fragment is coupled to the first fragment in the solid phase. Then, solution phase chemistry is then used to add additional amino acid material to a different third fragment. Subsequently, this different third fragment is coupled to the coupled first and different second fragment in the solution phase. The use of a pseudoproline in one of the fragments eases solid phase synthesis of that fragment and also eases subsequent solution phase coupling of this fragment to the other fragments. The present invention is very useful for forming insulinotropic peptides such as GLP-1(7-36) and its natural and non-natural counterparts.

Abstract translation: 本发明涉及使用固相和溶液相（“混合”）方法合成的促胰岛素肽的制备。 通常，该方法包括使用固相化学合成三种不同的肽中间体片段。 然后使用溶液相化学为第三片段添加另外的氨基酸材料，然后将其与第二片段偶联，然后与溶液中的第一片段偶联。 或者，不同的第二片段与固相中的第一片段偶联。 然后，然后使用溶液相化学法将另外的氨基酸材料添加到不同的第三片段。 随后，将该不同的第三片段与溶液相中的偶联的第一和不同的第二片段偶联。 在其中一个片段中使用假脯氨酸使得该片段的固相合成减轻了该片段随后与其它片段的溶液相偶联。 本发明对于形成促胰岛素肽如GLP-1（7-36）及其天然和非天然对应物非常有用。

公开(公告)号：US20090085919A1

公开(公告)日：2009-04-02

申请号：US11864484

申请日：2007-09-28

Applicant: Lin Chen ,  Junhong Sun ,  Guofang Jiao ,  Chihong Zhang ,  Lingjun Chen

Inventor： Lin Chen ,  Junhong Sun ,  Guofang Jiao ,  Chihong Zhang ,  Lingjun Chen

IPC: G06F13/14 ,  G09G5/36

CPC classification number: G06T15/005 ,  G06F8/441

Abstract: The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.

Abstract translation: 本公开包括将着色器变量映射到物理寄存器的系统和方法。 在一个实施例中，公开了一种图形处理单元（GPU）和耦合到GPU的存储器。 存储器包括具有寄存器文件部分的处理器可读数据文件。 寄存器文件部分具有包括多个数据项的矩形结构。 与着色器程序的数据元素对应的多个数据项中的至少两个。 数据元素具有不同的数据存储类型。

公开(公告)号：US07487378B2

公开(公告)日：2009-02-03

申请号：US11231078

申请日：2005-09-19

Applicant: Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

Inventor： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC classification number: H04L7/02 ,  H04L7/0025 ,  H04L7/0091

Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract translation: 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

公开(公告)号：US20080005455A1

公开(公告)日：2008-01-03

申请号：US11804413

申请日：2007-05-17

Applicant: Joseph Macri ,  Steven Morein ,  Ming-Ju Lee ,  Lin Chen

Inventor： Joseph Macri ,  Steven Morein ,  Ming-Ju Lee ,  Lin Chen

IPC: G06F12/08 ,  G06F1/12

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

Abstract translation: 描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。

公开(公告)号：US20070179279A1

公开(公告)日：2007-08-02

申请号：US11646779

申请日：2006-12-28

Applicant: Lin Chen ,  Christopher Roberts

Inventor： Lin Chen ,  Christopher Roberts

IPC: C07K1/02

CPC classification number: C07K14/665 ,  C07K1/02 ,  C07K1/026 ,  C07K1/04 ,  C07K1/1075 ,  C07K5/06139 ,  C07K5/0817

Abstract: Methods for the synthesis of arginine-containing peptides are provided. The methods include a step that minimizes contact of side chain protected arginine with base prior to the coupling step.

Abstract translation: 提供了含有精氨酸的肽的合成方法。 所述方法包括在偶联步骤之前使侧链保护的精氨酸与碱的接触最小化的步骤。