公开(公告)号：US5640122A

公开(公告)日：1997-06-17

申请号：US464551

申请日：1995-06-05

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G05F3/20 ,  G05F3/26 ,  H02J1/00

CPC分类号： G05F3/205 ,  G05F3/262

摘要： A bias circuit for generating a bias voltage that tracks power supply voltage variations, and that is compensated for variations in p-channel transistor and process parameters, is disclosed. The bias circuit includes a voltage divider, such as a resistor divider, that produces a ratioed voltage based on the power supply voltage to be tracked. The ratioed voltage is applied to a first input of a differential stage, the output of which is applied to an intermediate stage including a drive transistor and a load; the second input of the differential stage receives a feedback voltage from an intermediate node that is connected to the source of a p-channel modulating transistor that has its gate biased so as to be in saturation, for example at ground. The current conducted by the p-channel modulating transistor depends upon the ratioed voltage from the voltage divider, and also on its transistor characteristics. This current is applied, via an output stage, to produce a reference voltage that tracks power supply voltage variations. This reference voltage may be applied, individually or in combination with an n-channel compensated reference voltage, to an output buffer to control output drive slew rates, or to a current source.

摘要翻译： 公开了一种用于产生跟踪电源电压变化并且被补偿了p沟道晶体管和工艺参数中的变化的偏置电压的偏置电路。 偏置电路包括诸如电阻器分压器的分压器，其基于待跟踪的电源电压产生比率电压。 将比率电压施加到差分级的第一输入，其输出被施加到包括驱动晶体管和负载的中间级; 差分级的第二输入接收来自中间节点的反馈电压，该中间节点连接到其栅极偏置为饱和的p沟道调制晶体管的源，例如在地。 由p沟道调制晶体管传导的电流取决于来自分压器的比例电压，以及其晶体管特性。 该电流经由输出级施加以产生跟踪电源电压变化的参考电压。 该参考电压可以单独地或与n沟道补偿参考电压组合施加到输出缓冲器以控制输出驱动转换速率，或者施加到电流源。

公开(公告)号：US5627793A

公开(公告)日：1997-05-06

申请号：US413789

申请日：1995-03-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C7/22 ,  G11C11/417 ,  H01L27/10 ,  G11C13/00

CPC分类号： G11C7/22 ,  G11C7/06

摘要： A method and circuit for significantly reducing a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device. An output of a first circuit is connected to a data line. The first circuit is designed with elements having a selected set of design parameters, such as transistor dimensions and transistor orientation. A second circuit is connected to the data line and also receives a clock signal generated by a signal delay circuit. The signal delay circuit receives an output enable signal, and after a delay period, produces the clock signal in response to the output enable signal. At least a portion of the signal delay circuit utilizes elements having the selected set of design parameters utilized in the first circuit. Thus, as process variations affect the electrical properties and the speed of the transistors in the first circuit, the same process variations will proportionately affect the electrical properties and speed of transistors in the delay circuit. This automatically compensates for process-induced speed variations and eliminates the need for a time margin when providing a clock signal for clocking an output of a first circuit into the input of a second circuit.

摘要翻译： 一种用于显着减少添加到时钟信号中的延迟的方法和电路，所述时钟信号将第一电路的输出定时成半导体器件中的第二电路的输入。 第一电路的输出连接到数据线。 第一电路设计有具有选定的一组设计参数的元件，例如晶体管尺寸和晶体管取向。 第二电路连接到数据线，并且还接收由信号延迟电路产生的时钟信号。 信号延迟电路接收输出使能信号，并且在延迟周期之后，响应于输出使能信号产生时钟信号。 信号延迟电路的至少一部分利用在第一电路中使用的具有所选择的一组设计参数的元件。 因此，随着工艺变化影响第一电路中的晶体管的电性能和速度，相同的工艺变化将成比例地影响延迟电路中的晶体管的电性能和速度。 这自动补偿过程引起的速度变化，并且当提供用于将第一电路的输出计时到第二电路的输入的时钟信号时，不需要时间裕度。

公开(公告)号：US5612918A

公开(公告)日：1997-03-18

申请号：US582424

申请日：1995-12-29

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC分类号： G11C29/785 ,  G11C29/24 ,  G11C29/80 ,  G11C29/808 ,  G11C29/84

摘要： A redundancy structure having fewer pass gates in the redundant decoder for quicker access to a redundant columns and a reduction in the complexity of the redundancy structure.

摘要翻译： 在冗余解码器中具有较少传输门的冗余结构，用于更快地访问冗余列并降低冗余结构的复杂度。

公开(公告)号：US5594373A

公开(公告)日：1997-01-14

申请号：US359397

申请日：1994-12-20

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： H03K19/0175 ,  G05F1/46 ,  G11C11/407 ,  H03K19/0185 ,  H03K19/0948 ,  H03B21/00

CPC分类号： H03K19/018585 ,  G05F1/465

摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

摘要翻译： 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5590307A

公开(公告)日：1996-12-31

申请号：US711

申请日：1993-01-05

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F12/08 ,  G11C8/16 ,  G11C11/401 ,  G11C11/41

CPC分类号： G06F12/0853 ,  G06F12/0879 ,  G11C8/16

摘要： A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.

摘要翻译： 提供双端口数据高速缓存，其具有专用于服务本地处理器的一个端口和专用于维护系统的第二端口。 通过将双端口数据高速缓存置于“突发模式”中，双端口数据高速缓存还能够高速传输一行或多条条目。 可以在读取或写入操作中使用突发模式。 初始地址在内部被锁存，并且在整个数据传输期间，存储器阵列中的字线被激活。 利用控制电路来循环访问多个列地址，而不必为每个操作提供单独的地址。

公开(公告)号：US5589783A

公开(公告)日：1996-12-31

申请号：US282177

申请日：1994-07-29

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/018585 ,  H03K19/0027

摘要： According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.

摘要翻译： 根据本发明，集成电路器件能够通过对器件进行最小的改变来响应多于一个的输入阈值电压电平。 集成电路装置的输入缓冲器被修改为可由可由若干不同控制装置产生的控制输入信号控制的可编程缓冲器。 这种控制装置包括接合选项，掩模选项，熔丝选项，寄存器选项和电压检测器选项。

公开(公告)号：US5577051A

公开(公告)日：1996-11-19

申请号：US173197

申请日：1993-12-22

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C29/02 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C11/41

摘要： According to the present invention, after a test data pattern has been written to selected static memory cells, the wordlines of the memory cells are turned off and the bitline true and bitline complement of the memory cells are simultaneously pulled to a predetermined logic level for the duration of the long write test so that the memory cells are disturbed. After the long write test, the contents of the memory cells are read to determine which memory cells contain corrupted data and therefore have bitline to memory cell leakage problems.

摘要翻译： 根据本发明，在将测试数据模式写入所选择的静态存储单元之后，关闭存储单元的字线，并将存储单元的位线真和位线补码同时拉至预定的逻辑电平 长写入测试的持续时间，使得存储器单元受到干扰。 在长写入测试之后，读取存储器单元的内容以确定哪些存储器单元包含损坏的数据，因此具有存储单元泄漏问题的位线。

公开(公告)号：US5576656A

公开(公告)日：1996-11-19

申请号：US414103

申请日：1995-03-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G05F3/24 ,  G05F1/46 ,  G05F1/56 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03F3/45 ,  G05F1/10

CPC分类号： H03F3/45479 ,  G05F1/465 ,  H03F3/45766 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45504 ,  H03F2203/45508

摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses. A sink current path circuit, according to various alternatives, is disclosed as providing an additional sink current path in the event that the limited output high voltage, or reference voltage, exceeds the desired level.

摘要翻译： 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了一种用于产生有限输出高电压或用于产生用于施加到除输出缓冲器之外的电路并且需要吸收电流的参考电压的电压基准和调节器电路。 电压参考和调节器基于电流镜，其中电流镜中的电流之和由偏置电流源控制，偏置电流源可以在操作周期内动态控制或通过熔丝进行编程。 根据各种替代方案，汇流电流路径电路被公开为在有限输出高电压或参考电压超过期望水平的情况下提供额外的灌电流通路。

公开(公告)号：US5574688A

公开(公告)日：1996-11-12

申请号：US438903

申请日：1995-05-10

申请人： David C. McClure ,  Thomas Teel

发明人： David C. McClure ,  Thomas Teel

IPC分类号： G11C29/00 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C29/84

摘要： A memory device, which communicates with external address and data buses, includes a circuit for mapping a redundant memory column having a redundant memory cell to an address of a defective memory column. An enable line communicates with the redundant memory column and selectively carries active and inactive signal levels for respectively enabling and disabling communication between the data bus and the redundant memory cell. An address decoder receives an address signal on the address bus and generates the active level on the enable line when the value of the address signal equals the address of the defective memory cell. A driver precharges the enable line to the inactive level while the address signal is invalid.

摘要翻译： 与外部地址和数据总线通信的存储器件包括用于将具有冗余存储器单元的冗余存储器列映射到有缺陷的存储器列的地址的电路。 使能线与冗余存储器列通信，并选择性地承载有源和非活动信号电平，以分别启用和禁用数据总线与冗余存储单元之间的通信。 地址解码器在地址总线上接收地址信号，并且当地址信号的值等于有缺陷的存储单元的地址时，在使能线上产生有效电平。 当地址信号无效时，驱动器将使能线路预充电到无效电平。

公开(公告)号：US5572456A

公开(公告)日：1996-11-05

申请号：US114747

申请日：1993-08-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F12/08 ,  H03K19/08 ,  G11C15/04

CPC分类号： G06F12/0895 ,  H03K19/08

摘要： A system for providing a CMOS NOR function that is distributed across a number of devices located on different chips. Specifically the present invention may be implemented in tag RAMs to provide expanded addressing. In other words, larger addresses may be processed using the present invention. This function is provided by using some transistors on each chip as part of the CMOS NOR gate. The tag RAM includes: a first input for receiving a first portion of an address, a second input for receiving a second portion of the address; a memory array connected to the first input; a comparator connected to the memory array and the second input, wherein the comparator has an output that produces an output signal in response to receiving a first signal from the second input and a second signal from the memory array; a first transistor having a gate connected to the output of the comparator, a first source/drain connected to a first pin, and a second source/drain connected to a second pin; and a second transistor having a gate connected to the output of the comparator, a first source/drain connected to the output pin, a second source/drain connected to a lower power supply voltage source.

摘要翻译： 一种用于提供分布在位于不同芯片上的多个设备的CMOS NOR功能的系统。 具体地，本发明可以在标签RAM中实现以提供扩展寻址。 换句话说，可以使用本发明来处理较大的地址。 该功能通过在每个芯片上使用一些晶体管作为CMOS或非门的一部分来提供。 标签RAM包括：用于接收地址的第一部分的第一输入端，用于接收地址的第二部分的第二输入; 连接到第一输入的存储器阵列; 连接到存储器阵列和第二输入的比较器，其中所述比较器具有响应于从所述第二输入接收第一信号和来自所述存储器阵列的第二信号而产生输出信号的输出; 第一晶体管，其具有连接到比较器的输出的栅极，连接到第一引脚的第一源极/漏极和连接到第二引脚的第二源极/漏极; 以及第二晶体管，具有连接到所述比较器的输出的栅极，连接到所述输出引脚的第一源极/漏极，连接到较低电源电压源的第二源极/漏极。