公开(公告)号：US06864188B2

公开(公告)日：2005-03-08

申请号：US10454518

申请日：2003-06-04

申请人： Matthias Goldbach

发明人： Matthias Goldbach

IPC分类号： H01L21/3065 ,  H01L21/033 ,  H01L21/302 ,  H01L21/308 ,  H01L21/311

CPC分类号： H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31144

摘要： To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or into an etching gas. The additional substance is present in the mask layer or a concentration of the additional substance can be subsequently increased in the mask layer. During a subsequent etching process for patterning using the mask layer, the mask layer is removed at a reduced etching rate.

摘要翻译： 为了提高耐腐蚀性和降低含硅掩模层的蚀刻速率，将另外的物质混入掩模层或蚀刻气体中。 另外的物质存在于掩模层中，或者可以在掩模层中随后增加附加物质的浓度。 在随后的使用掩模层进行图案化的蚀刻工艺中，以降低的蚀刻速率除去掩模层。

公开(公告)号：US06861312B2

公开(公告)日：2005-03-01

申请号：US10233969

申请日：2002-09-03

申请人： Albert Birner ,  Matthias Goldbach ,  Joern Luetzen

发明人： Albert Birner ,  Matthias Goldbach ,  Joern Luetzen

IPC分类号： H01L21/334 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242

CPC分类号： H01L21/76232 ,  H01L21/763 ,  H01L27/1087 ,  H01L29/66181

摘要： An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to be formed, in particular, a base region thereof. At least part of the widened region is then provided with a material region for the insulation region.

摘要翻译： 通过首先加宽待形成的沟槽的第一沟槽区域，特别是其基极区域，形成用于DRAM的沟槽结构中的绝缘区域，例如氧化物环。 然后至少部分加宽区域设置有用于绝缘区域的材料区域。

公开(公告)号：US06559069B2

公开(公告)日：2003-05-06

申请号：US10215151

申请日：2002-08-08

申请人： Matthias Goldbach ,  Albert Birner

发明人： Matthias Goldbach ,  Albert Birner

IPC分类号： H01L2131

CPC分类号： H01L27/1087 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/3063 ,  H01L21/31675 ,  H01L29/66181

摘要： In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.