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42 条记录 (耗时 0.016 秒)

    Method and layout of semiconductor device with reduced parasitics
    3.
    发明授权
    Method and layout of semiconductor device with reduced parasitics 有权

    公开(公告)号：US07928481B2

    公开(公告)日：2011-04-19

    申请号：US11828944

    申请日：2007-07-26

    申请人： Albert Birner ,  Qiang Chen

    发明人： Albert Birner ,  Qiang Chen

    IPC分类号： H01L29/76

    摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

    Method for Producing an Electrically Conductive Connection
    4.
    发明申请
    Method for Producing an Electrically Conductive Connection 有权
    导电连接方法

    公开(公告)号：US20100279503A1

    公开(公告)日：2010-11-04

    申请号：US12433033

    申请日：2009-04-30

    申请人： Uwe Seidel ,  Thorsten Obernhuber ,  Albert Birner ,  Georg Ehrentraut

    发明人： Uwe Seidel ,  Thorsten Obernhuber ,  Albert Birner ,  Georg Ehrentraut

    IPC分类号： H01L21/768 ,  B05D5/12

    CPC分类号： H01L21/76898

    摘要： A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate.

    摘要翻译： 一种用于在半导体衬底的第一表面和半导体衬底的第二表面之间制造导电连接的方法包括制造一个孔，形成包括钨的导电层，从半导体的第一表面去除导电层 衬底，用铜填充孔并使半导体衬底变薄。 该孔由半导体衬底的第一表面制成半导体衬底。 从半导体衬底的第一表面去除导电层，其中导电层在孔中至少具有减小的厚度。 半导体衬底从半导体衬底的第一表面的相对表面的表面开始变薄，以获得在半导体衬底的第二表面处未被覆盖的半导体衬底的第二表面。

    Method and Layout of Semiconductor Device with Reduced Parasitics
    5.
    发明申请
    Method and Layout of Semiconductor Device with Reduced Parasitics 有权
    具有减少寄生性的半导体器件的方法和布局

    公开(公告)号：US20090026539A1

    公开(公告)日：2009-01-29

    申请号：US11828944

    申请日：2007-07-26

    申请人： Albert Birner ,  Qiang Chen

    发明人： Albert Birner ,  Qiang Chen

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/7823

    摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

    摘要翻译： 公开了一种半导体器件。 该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。 还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。 栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。 绝缘区域设置在栅极连接下方的半导体本体上。

    Method of forming a silicon dioxide layer
    7.
    发明授权
    Method of forming a silicon dioxide layer 失效
    形成二氧化硅层的方法

    公开(公告)号：US07081384B2

    公开(公告)日：2006-07-25

    申请号：US10823607

    申请日：2004-04-14

    申请人： Albert Birner ,  Matthias Goldbach ,  Irene Sperl

    发明人： Albert Birner ,  Matthias Goldbach ,  Irene Sperl

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1087 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/3063 ,  H01L21/31662 ,  H01L27/10832 ,  Y10S438/964

    摘要： The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a semiconductor substrate having at least one monocrystalline silicon surface region having a curved surface, roughening the surface of the at least one monocrystalline silicon surface region to produce a layer of porous silicon, and thermally oxidizing the at least one roughened monocrystalline silicon surface.

    摘要翻译： 本发明涉及通过热氧化半导体衬底上的至少一个单晶硅表面区域来形成二氧化硅层的方法。 硅表面区域具有曲面。 该方法可以包括提供具有至少一个具有弯曲表面的单晶硅表面区域的半导体衬底，使至少一个单晶硅表面区域的表面粗糙化以产生多孔硅层，并热氧化至少一个粗糙化单晶 硅表面。

    Memory cell and method for fabricating it
    8.
    发明申请
    Memory cell and method for fabricating it 有权
    记忆单元及其制造方法

    公开(公告)号：US20050158945A1

    公开(公告)日：2005-07-21

    申请号：US10980069

    申请日：2004-11-03

    申请人： Albert Birner ,  Matthias Foerster ,  Thomas Hecht ,  Michael Stadtmueller ,  Andreas Orth

    发明人： Albert Birner ,  Matthias Foerster ,  Thomas Hecht ,  Michael Stadtmueller ,  Andreas Orth

    IPC分类号： H01L21/8239 ,  H01L21/334 ,  H01L21/8229 ,  H01L21/8242 ,  H01L29/94

    CPC分类号： H01L29/66181 ,  H01L29/945

    摘要： The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).

    摘要翻译： 本发明提供了一种用于制造存储单元的方法，提供了一种衬底（101），蚀刻到衬底（101）中的沟槽型凹陷（102），在沟槽中非保形地沉积的阻挡层（103） 型凹陷（102），在沟槽型凹部（102）的内部区域上生长的晶粒元素（104），沉积在晶粒元素的表面上的介电层（202）和沟槽的内部区域 型凹陷，并且导电层沉积在电介质层上，晶粒元素（104）选择性地生长在形成下部区域的电极区域（301）中的沟槽型凹陷（102）的内部区域（105） 的沟槽型凹陷（102）和在形成沟槽型凹陷（102）的上部区域的凸缘区域（302）中继续生长的非晶硅层。

    Semiconductor Device and Method of Making the Same
    9.
    发明申请
    Semiconductor Device and Method of Making the Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20140042537A1

    公开(公告)日：2014-02-13

    申请号：US13584581

    申请日：2012-08-13

    申请人： Albert Birner ,  Helmut Brech

    发明人： Albert Birner ,  Helmut Brech

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/167 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

    摘要翻译： 半导体器件包括在半导体本体的第一区域中的漂移区域。 漂移区域包括第一导电类型的掺杂剂。 至少在漂移区域的边缘附近形成掺杂剂延迟区域。 将第二导电类型的掺杂剂注入半导体本体。 将半导体体进行退火以形成体区，使得第二导电类型的掺杂剂以第一扩散速率被驱动到半导体本体中。 掺杂剂延迟区域防止掺杂剂以第一扩散速率扩散到漂移区域。

    Method and layout of semiconductor device with reduced parasitics
    10.
    发明授权
    Method and layout of semiconductor device with reduced parasitics 有权
    减少寄生效应的半导体器件的方法和布局

    公开(公告)号：US08492229B2

    公开(公告)日：2013-07-23

    申请号：US13087102

    申请日：2011-04-14

    申请人： Albert Birner ,  Qiang Chen

    发明人： Albert Birner ,  Qiang Chen

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/7823

    摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

    摘要翻译： 公开了一种半导体器件。 该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。 还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。 栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。 绝缘区域设置在栅极连接下方的半导体本体上。