公开(公告)号：US07084043B2

公开(公告)日：2006-08-01

申请号：US10792691

申请日：2004-03-05

申请人： Albert Birner ,  Steffen Breuer ,  Matthias Goldbach ,  Joern Luetzen ,  Dirk Schumann

发明人： Albert Birner ,  Steffen Breuer ,  Matthias Goldbach ,  Joern Luetzen ,  Dirk Schumann

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

摘要： A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.

摘要翻译： 在任何期望的几何形状的硅表面上制造绝缘体上硅层结构的方法可以局部地产生绝缘体上硅结构。 该方法包括在硅表面区域形成中孔，中孔表面的氧化形成硅单晶的硅氧化物和肋状区域; 以及执行选择性外延工艺，其中硅在相对于氧化硅区域选择性地在未覆盖的肋区域上生长。 肋区域保持在相邻的中孔之间的适当位置，一旦达到肋区域的预定的最小硅壁厚度，则该步骤结束，肋区域的露出，其布置在远离半导体衬底的相邻介孔之间的端部 。 该方法可用于制造具有这种类型的选择晶体管的垂直晶体管和存储单元。

公开(公告)号：US06861312B2

公开(公告)日：2005-03-01

申请号：US10233969

申请日：2002-09-03

申请人： Albert Birner ,  Matthias Goldbach ,  Joern Luetzen

发明人： Albert Birner ,  Matthias Goldbach ,  Joern Luetzen

IPC分类号： H01L21/334 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242

CPC分类号： H01L21/76232 ,  H01L21/763 ,  H01L27/1087 ,  H01L29/66181

摘要： An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to be formed, in particular, a base region thereof. At least part of the widened region is then provided with a material region for the insulation region.

摘要翻译： 通过首先加宽待形成的沟槽的第一沟槽区域，特别是其基极区域，形成用于DRAM的沟槽结构中的绝缘区域，例如氧化物环。 然后至少部分加宽区域设置有用于绝缘区域的材料区域。

公开(公告)号：US07208370B2

公开(公告)日：2007-04-24

申请号：US10484562

申请日：2002-07-08

申请人： Albert Birner ,  Joern Luetzen

发明人： Albert Birner ,  Joern Luetzen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876 ,  H01L29/66666

摘要： To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the side wall and the base. A semiconductor layer is deposited so that an epitaxial semiconductor layer grows on the side wall and a semiconductor layer grows on the base, with a space remaining between these layers. The semiconductor layers are covered with a thin dielectric, which partially limits a flow of current, and the space is filled. During a subsequent heat treatment, dopants diffuse out of the conductive material into the epitaxial semiconductor layer, where they form a doping region. The thin dielectric limits the diffusion of the dopants into the semiconductor substrate and prevents the propagation of crystal lattice defects into the epitaxial semiconductor layer.

摘要翻译： 为了制造垂直晶体管，设置沟槽，其沟槽由单晶形式的半导体衬底形成，其基底由多晶半导体衬底形成。 过渡区域设置在侧壁和底座之间。 沉积半导体层，使得外延半导体层在侧壁上生长并且半导体层在基底上生长，并且在这些层之间保留空间。 半导体层被薄的电介质覆盖，其部分地限制了电流，并且填充了空间。 在随后的热处理期间，掺杂剂从导电材料扩散到外延半导体层中，在其中它们形成掺杂区域。 薄电介质限制掺杂剂到半导体衬底中的扩散，并防止晶格缺陷向外延半导体层的传播。

公开(公告)号：US20060017132A1

公开(公告)日：2006-01-26

申请号：US11167946

申请日：2005-06-28

申请人： Albert Birner ,  Andreas Weber ,  Till Schloesser ,  Joern Luetzen

发明人： Albert Birner ,  Andreas Weber ,  Till Schloesser ,  Joern Luetzen

IPC分类号： H01L29/00

CPC分类号： H01L21/31612 ,  C23C16/345 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02131 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/3141 ,  H01L21/3185

摘要： The present invention relates to a method for producing a dielectric on a semiconductor body having the following steps that are to be performed successively: provision of a semiconductor body, application of a dielectric layer on at least parts of a first surface of the semiconductor body in such a way as at least partly to form an interface between the dielectric layer and the semiconductor body, and thermal annealing of the semiconductor body and the dielectric layer. The method according to the invention is distinguished by the fact that temporally prior to the annealing, for the purpose of improving the saturation and the electrical properties, fluorine-containing particles are introduced into regions of the semiconductor body and/or of the dielectric layer which adjoin the interface. The present invention furthermore relates to a corresponding semiconductor structure.

摘要翻译： 本发明涉及一种在半导体本体上制造电介质的方法，其具有以下步骤：连续进行：提供半导体本体，在半导体本体的第一表面的至少一部分上施加电介质层 这种方式至少部分地形成介电层和半导体本体之间的界面，以及半导体本体和电介质层的热退火。 根据本发明的方法的区别在于，在退火之前的时间上，为了提高饱和度和电性能，将含氟颗粒引入到半导体本体和/或电介质层的区域中，其中 毗邻接口。 本发明还涉及相应的半导体结构。

公开(公告)号：US07192830B2

公开(公告)日：2007-03-20

申请号：US10862818

申请日：2004-06-07

申请人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

发明人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

摘要： Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

摘要翻译： 将硅纳米晶体作为存储层（6）施加，并且使用间隔元件（11）相对于栅电极（5）横向去除。 通过掺杂剂的注入，源极/漏极区域（2）以相对于存储层（6）的自对准方式制造。 存储层（6）的部分被栅极（5）和栅极电介质（4）中断，使得沟道区域（3）的中心部分不被存储层（6）覆盖。 该存储单元适合作为虚拟地面架构中的多位闪存单元。

公开(公告)号：US07074317B2

公开(公告)日：2006-07-11

申请号：US10436427

申请日：2003-05-12

申请人： Albert Birner ,  Dirk Schumann ,  Matthias Goldbach

发明人： Albert Birner ,  Dirk Schumann ,  Matthias Goldbach

IPC分类号： H05K3/07

CPC分类号： H01L21/3063 ,  C25F3/12 ,  H01L27/10861 ,  H01L28/40

摘要： An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 μm can be produced on p-doped silicon having a very low resistivity at a high etching rate.

摘要翻译： 提供电化学方法用于在p掺杂硅中制造用于大规模集成半导体存储器的非常高的直径/深度纵横比的沟槽电容器的沟槽。 可以以高蚀刻速率在具有非常低电阻率的p掺杂硅上产生直径小于约100nm且深度大于10um的沟槽（大孔）。

公开(公告)号：US20050014335A1

公开(公告)日：2005-01-20

申请号：US10862818

申请日：2004-06-07

申请人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

发明人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

摘要： Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

摘要翻译： 将硅纳米晶体作为存储层（6）施加，并且使用间隔元件（11）相对于栅电极（5）横向去除。 通过掺杂剂的注入，源极/漏极区域（2）以相对于存储层（6）的自对准方式制造。 存储层（6）的部分被栅极（5）和栅极电介质（4）中断，使得沟道区域（3）的中心部分不被存储层（6）覆盖。 该存储单元适合作为虚拟地面架构中的多位闪存单元。

公开(公告)号：US07268381B2

公开(公告)日：2007-09-11

申请号：US10486758

申请日：2002-07-12

申请人： Albert Birner ,  Matthias Goldbach ,  Till Schlösser

发明人： Albert Birner ,  Matthias Goldbach ,  Till Schlösser

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876

摘要： The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

摘要翻译： 沟槽电容器的上电容器电极通过管状的单晶Si接触形成区域连接到选择晶体管的外延生长的源极/漏极区域。 栅极电极层在晶体管周围具有椭圆形外围轮廓，存储单元的栅极电极层的椭圆形外围轮廓沿着字线排列成一行形成重叠区域，以增加堆积密度。

公开(公告)号：US06919255B2

公开(公告)日：2005-07-19

申请号：US10630373

申请日：2003-07-30

申请人： Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

发明人： Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

IPC分类号： H01L27/108 ,  H01L21/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

摘要翻译： 一种制造半导体沟槽结构的方法包括在半导体衬底中形成沟槽并用填充物填充沟槽。 具有第一最高温度的第一热处理固化填料。 从沟槽的上部区域移除填料至达边界表面限定了一个环形区域。 在具有不显着高于第一最高温度的第二最高温度的第二热处理中，衬套沉积在套环区域和边界表面上。 将衬垫从边界表面移除，从而暴露填料。 然后从沟槽的下部区域去除填料。

公开(公告)号：US06878600B2

公开(公告)日：2005-04-12

申请号：US10436426

申请日：2003-05-12

申请人： Albert Birner ,  Matthias Goldbach ,  Martin Franosch

发明人： Albert Birner ,  Matthias Goldbach ,  Martin Franosch

IPC分类号： H01L21/3063 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/1087

摘要： A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.

摘要翻译： 一种用于制造具有中孔的沟槽的沟槽电容器的方法，所述沟槽电容器适用于分立电容器和集成半导体存储器，显着增加了电容器的电极的表面积，并因此显着增加了其电容。 电化学地制造直径为约2〜50nm的小木蛾孔状通道的中孔。 因此，可以产生具有大的电容容积比的电容。 当介孔达到与另一个中孔或相邻沟槽的最小距离（自钝化）时，介孔的生长最终停止。 因此，可以以自我调节的方式避免在两个相邻介孔之间形成“短路”。 此外，提供一种半导体器件，其包括通过根据本发明的方法制造的半导体衬底的前侧上的至少一个沟槽电容器。