公开(公告)号：US06221560B1

公开(公告)日：2001-04-24

申请号：US09373244

申请日：1999-08-12

申请人： Choi Pheng Soo ,  Lap Chan

发明人： Choi Pheng Soo ,  Lap Chan

IPC分类号： G03C500

CPC分类号： H01L21/31053 ,  Y10S148/05

摘要： A new method for planarizing silicon dioxide surfaces in semiconductor structures. Starting with a structure of an underlying layer (for instance a layer of metal lines) a layer of oxide is deposited and profiled by positive tone imaging. A layer of PPMS is deposited. Using the mask of the starting structure, the PPMS layer is exposed changing the PPMS to PPMSO in the exposed regions. The unexposed PPMS is removed, the PPMSO (unexposed regions of the PPMS) are planarized, this planarization can proceed to the point where no more PPMSO is present (the PPMSO “columns” are removed together with the intra-layer of patterned oxide). The surface thus created shows excellent planarity, this surface can be further planarized down to the top level of the underlying pattern, if it is desirable to do so.

摘要翻译： 一种在半导体结构中平坦化二氧化硅表面的新方法。 从底层（例如一层金属线）的结构开始，通过正色成像沉积和分析氧化层。 存放一层PPMS。 使用起始结构的掩模，PPMS层暴露在暴露区域中将PPMS改变为PPMSO。 去除未曝光的PPMS，PPMSO（PPMS的未曝光区域）被平坦化，该平面化可以进行到不再存在PPMSO的点（与图案化氧化物层内的PPMSO“列”一起被去除）。 如此创建的表面显示出优异的平面度，如果希望这样做，则该表面可以进一步平坦化到底层图案的顶层。

公开(公告)号：US06214728B1

公开(公告)日：2001-04-10

申请号：US09196604

申请日：1998-11-20

申请人： Lap Chan ,  Sam Fong Yau Li ,  Hou Tee Ng

发明人： Lap Chan ,  Sam Fong Yau Li ,  Hou Tee Ng

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.

摘要翻译： 掺杂硅半导体衬底上的封装铜插头具有覆盖有绝缘体的衬底表面，其上形成有扩散阻挡层的插塞孔，孔形成在孔的顶部和顶部。 塞孔部分地填充有无电沉积的铜金属塞。 封装金属沉积物覆盖插塞，而不会发生任何中间氧化和降解。 在从铜到铜的共沉积物的转变中，封装的Pt，Pd和/或Ag金属在无电镀浴中沉积而不氧化和降解，然后纯化沉积包封金属层以堵住塞子。 封装金属沉积物的表面通过在插塞孔上方过度生长而形成，随后抛光绝缘体层的表面，从而去除通过CMP工艺抛光的金属层的过度生长，以使作为顶部表面的绝缘体层的表面平坦化 器件实现金属层与绝缘体层的形貌的共面性。

公开(公告)号：US06204137B1

公开(公告)日：2001-03-20

申请号：US09556386

申请日：2000-04-24

申请人： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

发明人： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/76224

摘要： A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

摘要翻译： 已经实现了形成MOS晶体管的新方法。 生长衬垫氧化物层。 沉积氮化硅层。 沟槽蚀刻为计划的STI。 在沟槽内生长沟槽衬垫。 沉积填充沟槽的沟槽氧化物层。 将沟槽氧化物层抛光以完成STI。 将相同的氮化硅层图案化以形成伪栅极。 沉积栅极衬垫层。 植入离子以形成轻掺杂的漏极结。 侧壁间隔件形成在与虚拟栅极电极和浅沟槽隔离件相邻处。 植入离子以形成漏极和源极结。 生长在源极和漏极结上方的外延硅层。 沉积金属层。 将外延硅层转化为硅化物以形成硅化源极和漏极触点。 将层间电介质层沉积并抛光到虚拟栅极。 蚀刻掉虚拟栅极以形成预定晶体管栅极的开口。 在晶体管栅极开口上沉积栅极氧化物层。 沉积栅极电极层以填充晶体管栅极开口。 图案化栅极电极层以完成晶体管栅极。

公开(公告)号：US6103594A

公开(公告)日：2000-08-15

申请号：US392393

申请日：1999-09-09

申请人： Alex See ,  Lap Chan

发明人： Alex See ,  Lap Chan

IPC分类号： H01L21/762 ,  H01L21/761

CPC分类号： H01L21/76229

摘要： A method of forming shallow trench isolations is achieved. STI structures so formed do not exhibit isolation oxide thinning due to dishing and erosion problems during the oxide CMP process. A silicon substrate is provided. A first dielectric layer is formed overlying the silicon substrate. A silicon nitride layer is deposited. The silicon nitride layer, the first dielectric layer, and the silicon substrate are etched to form trenches for planned shallow trench isolations. A second dielectric layer is deposited overlying the silicon nitride layer and the trenches. The second dielectric layer is etched to form sidewall spacers inside the trenches. A silicon layer is selectively grown overlying the silicon substrate only where the silicon substrate is exposed in the trenches, and wherein the step of growing is stopped before the silicon layer exceeds the top surface of the silicon nitride layer. A third dielectric layer is deposited overlying the silicon nitride layer, the sidewall spacers, and the silicon layer. The third dielectric layer is polished down to the top surface of the silicon nitride layer to complete the shallow trench isolations where the silicon nitride layer acts as a polishing stop, and the integrated circuit device is completed.

摘要翻译： 实现形成浅沟槽隔离的方法。 如此形成的STI结构在氧化物CMP工艺期间由于凹陷和侵蚀问题而不表现出隔离氧化物变薄。 提供硅衬底。 在硅衬底上形成第一介电层。 沉积氮化硅层。 蚀刻氮化硅层，第一介电层和硅衬底以形成用于规划的浅沟槽隔离的沟槽。 第二介质层沉积在氮化硅层和沟槽之上。 蚀刻第二电介质层以在沟槽内形成侧壁间隔物。 只有在硅衬底暴露在沟槽中的硅衬底上选择性地生长硅层，并且其中在硅层超过氮化硅层的顶表面之前停止生长步骤。 第三电介质层沉积在氮化硅层，侧壁间隔物和硅层上。 第三电介质层被抛光到氮化硅层的顶表面，以完成浅沟槽隔离，其中氮化硅层用作抛光停止，并且集成电路器件完成。

公开(公告)号：US6103569A

公开(公告)日：2000-08-15

申请号：US459730

申请日：1999-12-13

申请人： Kok Hin Teo ,  Feng Chen ,  Lap Chan

发明人： Kok Hin Teo ,  Feng Chen ,  Lap Chan

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76895

摘要： A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.

摘要翻译： 用于平面化用于器件互连的金属插头的方法。 该过程开始于在其上提供至少一个装置的半导体结构。 在器件和半导体结构上形成介电层。 在介电层上形成第一阻挡金属层，在第一阻挡金属层上形成牺牲氧化物层。 牺牲氧化物层，第一阻挡金属层和电介质层被图案化以形成接触开口。 在半导体结构上形成第二阻挡金属层，在第二阻挡金属层上形成金属接触层。 使用第一化学机械抛光工艺对金属接触层和第二阻挡金属层进行平面化处理，并去除牺牲氧化物层。 使用第二化学机械抛光工艺将金属接触层和第一阻挡金属层平坦化。

公开(公告)号：US6100196A

公开(公告)日：2000-08-08

申请号：US396254

申请日：1999-09-15

申请人： Lap Chan ,  Jia Zhen Zheng

发明人： Lap Chan ,  Jia Zhen Zheng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002

摘要： A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

摘要翻译： 描述了在集成电路中制造铜互连的方法。 该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。 通过两个阻挡层防止铜从连接器的扩散。 一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。 镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。 抛光。 由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

公开(公告)号：US5742088A

公开(公告)日：1998-04-21

申请号：US837486

申请日：1997-04-18

申请人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

发明人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L21/74 ,  H01L29/08 ,  H01L27/11 ,  H01L29/40

CPC分类号： H01L21/743

摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.

摘要翻译： 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。

公开(公告)号：US5728621A

公开(公告)日：1998-03-17

申请号：US845870

申请日：1997-04-28

申请人： Jia Zhen Zheng ,  Charlie Wee Song Tay ,  Wei Lu ,  Lap Chan

发明人： Jia Zhen Zheng ,  Charlie Wee Song Tay ,  Wei Lu ,  Lap Chan

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.

摘要翻译： 描述了形成平面化高质量氧化物浅沟槽隔离的新方法。 覆盖衬垫氧化物层的氮化物层设置在半导体衬底的表面上。 通过氮化物和衬垫氧化物层蚀刻多个隔离沟槽到半导体衬底中，其中在两个隔离沟槽之间存在至少一个第一宽氮化物区域和在另外两个隔离沟槽之间的至少一个第二窄氮化物区域。 在填充隔离沟槽的氮化物层上沉积高密度等离子体（HDP）氧化物层，其中HDP氧化物在宽氮化物层上的第一区域中更厚地沉积，并且在第二区域上更薄地沉积在窄氮化物层上，并且其中 在第一区域和覆盖隔离沟槽的区域之间的HDP氧化物的阶跃高度的差异是第一高度。 在HDP氧化物层上涂覆一层旋涂玻璃，其中在第一区域和覆盖隔离沟槽的区域之间的旋涂玻璃材料的阶梯高度的差异是比第一高度小的第二高度。 旋转玻璃层和第一区域中的HDP氧化物层的部分被蚀刻掉。 抛光剩余的旋涂玻璃层和HDP氧化物层，其中衬底被平坦化。

公开(公告)号：US5693178A

公开(公告)日：1997-12-02

申请号：US559050

申请日：1996-01-18

申请人： Lap Chan ,  Simon Chooi

发明人： Lap Chan ,  Simon Chooi

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L22/34

摘要： A microloading quantification apparatus is comprising a supporting substrate, a first bonding pad deposited upon the supporting substrate, a second bonding pad deposited upon the supporting substrate, and an etched conductive pattern deposited upon the supporting substrate and operably connected to the first bonding pad and the second bonding pad. Methods for the formation and application of the microloading quantification apparatus to quantify the variation of the microloading effect as a result of modifications of the set of parameters of integrated circuit processing particularly those of the plasma dry etch are described.

摘要翻译： 微量负载量化装置包括支撑衬底，沉积在支撑衬底上的第一焊盘，沉积在支撑衬底上的第二焊盘，以及沉积在支撑衬底上并可操作地连接到第一焊盘和 第二粘接垫。 描述了形成和应用微量负荷量化装置的方法，以量化由于集成电路处理的一组参数，特别是等离子体干蚀刻的参数组的修改而导致的微加载效应的变化。

公开(公告)号：US5627094A

公开(公告)日：1997-05-06

申请号：US566809

申请日：1995-12-04

申请人： Lap Chan ,  Yeow M. Teo

发明人： Lap Chan ,  Yeow M. Teo

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/40 ,  H01L21/76895 ,  H01L27/0629 ,  H01L27/108 ,  H01L28/60 ,  H01L28/82 ,  H01L28/90

摘要： A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer. Finally, the filled isotropically etched aperture is planarized until there is exposed a flange of the first polysilicon layer formed into the ledge.

摘要翻译： 一种用于形成集成电路内使用的层叠容器电容器的方法。 连续形成在半导体衬底上的是第一电介质层，第二电介质层和图案化掩模层。 在各向同性蚀刻工艺中，第一介电层比第二介电层慢。 通过使用图案化掩模层作为掩模的各向异性蚀刻工艺，至少部分地蚀刻孔，穿过第一介电层。 通过使用图案化掩模层作为掩模的各向同性蚀刻工艺，蚀刻第二介电层以产生形成在第一介电层上方并在图案化掩模层下方的凸缘。 然后去除图案化的掩模层。 然后形成各向异性和各向异性蚀刻的孔径是第一多晶硅层，第三介电层和第二多晶硅层。 最后，填充的各向同性蚀刻的孔被平坦化，直到暴露出形成在凸缘中的第一多晶硅层的凸缘。