摘要:
A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA and a first-second PA, and a second PA block having a second-first PA and a second-second PA. First and second modulated switchers are adapted to selectively supply power to the first-first PA and the second-first PA, and to supply power to the first-second PA and the second-second PA, respectively. The first and second modulated switchers have a modulation bandwidth of at least 20 MHz and are both suitable for envelope tracking modulation. A control system is adapted to selectively enable and disable the first-first PA, first-second PA, the second-first PA, and the second-second PA. First and second switches are responsive to control signals to route carriers and received signals between first and second antennas depending upon a selectable mode of operation such as intra-band or inter-band operation.
摘要:
Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a VRAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.
摘要:
A front end radio architecture (FERA) is disclosed that includes a power amplifier (PA). The PA includes first and second input terminals and first and second output terminals and a PA die having first and second half amplifier cells, each of which includes an output amplifier stage. The first and second half amplifier cells are coupled to the first and second input terminals. First and second PA transformers each include first, second, and third windings. The first windings are coupled to the output amplifier stages. The second winding of the first PA transformer is coupled to the first output terminal of the PA and also coupled in series with the second winding of the second PA transformer. The third winding of the first PA transformer is coupled in series with the third winding of the second PA transformer, with one end of the second PA transformer being coupled to the second output terminal of the PA.
摘要:
An envelope tracking power supply and transmitter control circuitry are disclosed. The transmitter control circuitry receives a first envelope power supply control signal and a second envelope power supply control signal. The envelope tracking power supply operates in one of a group of operating modes, which includes a first operating mode and a second operating mode. During both the first operating mode and the second operating mode, a first envelope power supply signal is provided to a driver stage based on the first envelope power supply control signal. During the first operating mode, a second envelope power supply signal is provided to a final stage based on the first envelope power supply control signal. However, during the second operating mode, the second envelope power supply signal is provided to the final stage based on the second envelope power supply control signal.
摘要:
A half-bandwidth based quadrature analog-to-digital converter (ADC) includes in-phase circuitry, quadrature-phase circuitry, and digital complex processing circuitry. The in-phase circuitry includes an in-phase pair of ADCs, which provide an in-phase pair of sub-quadrature output signals, based on an analog in-phase input signal. Similarly, the quadrature-phase circuitry includes a quadrature-phase pair of ADCs, which provide a quadrature-phase pair of sub-quadrature output signals based on an analog quadrature-phase input signal. The digital complex processing circuitry combines, filters, and restructures the in-phase pair of sub-quadrature output signals and the quadrature-phase pair of sub-quadrature output signals to provide a digital in-phase output signal and a digital quadrature-phase output signal. Each of the in-phase pair of ADCs has about an ADC bandwidth. The in-phase circuitry has an input bandwidth, which is about equal to two times the ADC bandwidth in one embodiment of the in-phase circuitry.
摘要:
The present disclosure relates to down conversion circuitry that uses a fast DC correction method to correct for a DC offset of an RF mixer and a post mixer amplifier. The down conversion circuitry may include a DC correction amplifier downstream of the post mixer amplifier to apply a DC correction, which is based on a gain of the post mixer amplifier. During a calibration mode, the DC offset of the RF mixer and the post mixer amplifier are determined at multiple gain levels of the post mixer amplifier. The DC correction needed at multiple gain levels of the post mixer amplifier is then determined based on the determined DC offset. During a normal operation mode, a desired gain of the post mixer amplifier is selected and a determined DC correction that correlates with the desired gain is provided.
摘要:
A power management system for a multi-carriers transmitter is disclosed. The power management system includes a first switcher having a control input and a power output, and a second switcher having a control input and a power output. Also included is a mode switch having a mode control input, wherein the mode switch is adapted to selectively couple the power output of the first switcher to the power output of the second switcher in response to a mode control signal received by the mode control input. Further included is a control system adapted to generate the mode control signal. The control system is coupled to the mode control input of the mode switch.
摘要:
The present invention relates to estimating a direct current (DC) offset of a radio frequency (RF) receiver when an estimated amplitude of a continuous-transmission amplitude-modulated (AM) RF signal is below a first threshold and when the RF receiver is not receiving an RF input signal. The estimated DC offset of the RF receiver may be used to improve RF receiver performance, particularly over temperature and supply voltage variations. Estimating the DC offset of the RF receiver when the estimated instantaneous amplitude of the continuous-transmission AM RF signal is below the first threshold may minimize errors in the estimated DC offset.
摘要:
A power management system for a radio frequency (RF) power amplifier (PA) load is disclosed. The power management system includes a first switching power supply that is adapted to output a relatively constant voltage, an electronic switch for selectively coupling the first switching power supply to the RF PA load, and a second switching power that is adapted to output a dynamic DC voltage to the RF PA load. The power management system further includes a control system that is adapted to close the electronic switch to supply the relatively constant DC voltage in addition to the dynamic DC voltage to the RF PA load in a first mode and to open the electronic switch wherein the relatively constant DC voltage is not supplied to the RF PA load in a second mode.
摘要:
The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.