公开(公告)号：US10983552B2

公开(公告)日：2021-04-20

申请号：US16507904

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F1/10 ,  G06F13/42 ,  G06F13/362

Abstract: Systems, methods, and apparatus for improving bus latency are described. Clock-cycle overhead associated with the transmission of trigger activation information may be reduced through the use of optimized datagram structures for register-configurable trigger activation mechanisms. A first mechanism defines a command code with a first Trigger-Activation datagram, and a second mechanism defines a command code with a second Trigger-Activation datagram that uses a 4-bit Magic-ID and eliminates 18 clock cycles from the conventional Extended Register Write datagram structure. A method performed at a device coupled to a serial bus includes generating a datagram that does not have an address field, populating a data payload of the datagram with trigger activation information directed to a plurality of slave devices coupled to a serial bus, and transmitting the datagram over the serial bus. Transmission of the datagram serves as a trigger that causes a configuration change in at least one slave device.

公开(公告)号：US10963035B2

公开(公告)日：2021-03-30

申请号：US16155824

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  James Lionel Panian ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/3234 ,  G06F13/40 ,  G06F13/10 ,  G06F1/3206

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

公开(公告)号：US10693674B2

公开(公告)日：2020-06-23

申请号：US15882494

申请日：2018-01-29

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

IPC: H04L12/40 ,  G06F13/42 ,  H04L25/49 ,  H04L1/16

Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.

公开(公告)号：US10572438B1

公开(公告)日：2020-02-25

申请号：US16295046

申请日：2019-03-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun ,  Radu Pitigoi-Aron

IPC: G06F13/42 ,  G06F1/10 ,  H04L12/40 ,  H04L12/403 ,  G06F1/12 ,  G06F1/08

Abstract: Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.

公开(公告)号：US10528503B1

公开(公告)日：2020-01-07

申请号：US16036416

申请日：2018-07-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/00 ,  G06F13/366 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

公开(公告)号：US10447464B2

公开(公告)日：2019-10-15

申请号：US16173949

申请日：2018-10-29

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Elisha Ulmer

IPC: H04L12/40 ,  H04L7/033

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

公开(公告)号：US10423551B2

公开(公告)日：2019-09-24

申请号：US15698191

申请日：2017-09-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Helena Deirdre O'Shea ,  Richard Dominic Wietfeldt

IPC: G06F13/28 ,  H04W28/06 ,  H04L29/06 ,  G06F13/42

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

公开(公告)号：US10417161B2

公开(公告)日：2019-09-17

申请号：US16219698

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'Shea ,  Lalan Jee Mishra ,  Amit Gil ,  Gary Chang ,  Mohit Kishore Prasad ,  Richard Dominic Wietfeldt ,  Vinay Jain

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

公开(公告)号：US10402365B2

公开(公告)日：2019-09-03

申请号：US16201369

申请日：2018-11-27

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/364 ,  H04L5/00

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.

公开(公告)号：US10310585B2

公开(公告)日：2019-06-04

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F13/40 ,  H01L23/29 ,  H04L12/931

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.