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公开(公告)号：US08705307B2
公开(公告)日：2014-04-22
申请号：US13298587
申请日：2011-11-17
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C2211/4061
摘要： An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.
摘要翻译： 提供的实施例是具有动态刷新的存储器系统，其包括具有存储器单元的存储器件。 该系统还包括与存储器设备和存储器控制器通信的刷新模块，该刷新模块被配置用于从存储器控制器接收刷新命令，并且响应于接收到所述存储器控制器来刷新存储器设备中的多个存储器单元 刷新命令。 响应于接收到刷新命令刷新的存储器单元的数量响应期望带宽特性和期望延迟特性中的至少一个。
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92.发明授权Method and apparatus for performing refresh operations in high-density memories 失效用于在高密度存储器中执行刷新操作的方法和装置公开(公告)号：US08635401B2
公开(公告)日：2014-01-21
申请号：US13453328
申请日：2012-04-23
申请人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Steven Powell , Jeffrey A. Stuecheli
发明人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Steven Powell , Jeffrey A. Stuecheli
IPC分类号： G06F13/10
CPC分类号： G11C11/40603
摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.
摘要翻译： 公开了一种执行刷新操作的方法。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。
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公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
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94.发明申请公开(公告)号：US20120054374A1
公开(公告)日：2012-03-01
申请号：US12869535
申请日：2010-08-26
IPC分类号： G06F3/00
CPC分类号： G06F11/3442 , G06F11/3476 , G06F2201/88 , G06F2201/885
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring access to a memory unit, updating an activity cache associated with an incrementor with access data corresponding to accesses to the memory unit, monitoring a rate of access to the memory unit, adjusting a sample rate of the access data for storage in the memory unit based on the rate of access, and scaling a value of the access data based on the sample rate.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括监视对存储器单元的访问，使用与对存储器单元的访问相对应的访问数据来更新与增量器相关联的活动高速缓存，监视对存储器单元的访问速率，调整访问数据的采样率以便存储 基于访问速率的存储器单元，以及基于采样率来缩放访问数据的值。
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95.发明授权Access speculation predictor with predictions based on a domain indicator of a cache line 有权使用基于缓存行的域指示符的预测来访问推测预测器公开(公告)号：US08127106B2
公开(公告)日：2012-02-28
申请号：US12105464
申请日：2008-04-18
CPC分类号： G06F12/0862 , G06F12/0831 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.
摘要翻译： 接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，从第一数据请求中提取第一地址和域指示符。 第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。 基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态 在与所选FSM相关联的寄存器中。
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96.发明授权System and method for improving the page crossing performance of a data prefetcher 有权用于提高数据预取器的页面交叉性能的系统和方法公开(公告)号：US07689774B2
公开(公告)日：2010-03-30
申请号：US11697493
申请日：2007-04-06
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0897 , G06F2212/6024
摘要： A system and method for improving the page crossing performance of a data prefetcher is presented. A prefetch engine tracks times at which a data stream terminates due to a page boundary. When a certain percentage of data streams terminate at page boundaries, the prefetch engine sets an aggressive profile flag. In turn, when the data prefetch engine receives a real address that corresponds to the beginning/end of a new page, and the aggressive profile flag is set, the prefetch engine uses an aggressive startup profile to generate and schedule prefetches on the assumption that the real address is highly likely to be the continuation of a long data stream. As a result, the system and method minimize latency when crossing real page boundaries when a program is predominately accessing long streams.
摘要翻译： 提出了一种用于提高数据预取器的页面交叉性能的系统和方法。 预取引擎跟踪由于页面边界而导致数据流终止的时间。 当某个百分比的数据流在页边界终止时，预取引擎设置一个积极的配置文件标志。 反过来，当数据预取引擎接收到对应于新页面的开始/结束的真实地址并且设置了侵略性简档标志时，预取引擎使用积极的启动简档来生成和调度预取，假设 真实地址很可能是长数据流的延续。 因此，当程序主要访问长流时，系统和方法在跨越实际页边界时最小化延迟。
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97.发明申请Access Speculation Predictor with Predictions Based on a Domain Indicator of a Cache Line 有权基于高速缓存行的域指示器的预测的访问猜测预测器公开(公告)号：US20090327612A1
公开(公告)日：2009-12-31
申请号：US12105464
申请日：2008-04-18
CPC分类号： G06F12/0862 , G06F12/0831 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.
摘要翻译： 接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，从第一数据请求中提取第一地址和域指示符。 第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。 基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态 在与所选FSM相关联的寄存器中。
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98.发明申请System and Method for Improving the Page Crossing Performance of a Data Prefetcher 有权用于提高数据预取器的页面交叉性能的系统和方法公开(公告)号：US20080250208A1
公开(公告)日：2008-10-09
申请号：US11697493
申请日：2007-04-06
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0897 , G06F2212/6024
摘要： A system and method for improving the page crossing performance of a data prefetcher is presented. A prefetch engine tracks times at which a data stream terminates due to a page boundary. When a certain percentage of data streams terminate at page boundaries, the prefetch engine sets an aggressive profile flag. In turn, when the data prefetch engine receives a real address that corresponds to the beginning/end of a new page, and the aggressive profile flag is set, the prefetch engine uses an aggressive startup profile to generate and schedule prefetches on the assumption that the real address is highly likely to be the continuation of a long data stream. As a result, the system and method minimize latency when crossing real page boundaries when a program is predominately accessing long streams.
摘要翻译： 提出了一种用于提高数据预取器的页面交叉性能的系统和方法。 预取引擎跟踪由于页面边界而导致数据流终止的时间。 当某个百分比的数据流在页边界终止时，预取引擎设置一个积极的配置文件标志。 反过来，当数据预取引擎接收到对应于新页面的开始/结束的真实地址并且设置了侵略性简档标志时，预取引擎使用激进的启动简档来生成和调度预取，假设 真实地址很可能是长数据流的延续。 因此，当程序主要访问长流时，系统和方法在跨越实际页边界时最小化延迟。
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99.发明授权Data processing system, method and interconnect fabric having an address-based launch governor 失效具有基于地址的发射调速器的数据处理系统，方法和互连结构公开(公告)号：US07415030B2
公开(公告)日：2008-08-19
申请号：US11054910
申请日：2005-02-10
IPC分类号： H04L12/28
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813 , G06F12/0851
摘要： A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.
摘要翻译： 数据处理系统包括互连结构，受保护资源具有多个存储体，每个存储体各自与多个地址集合中的相应一个地址集相关联，控制对资源的访问的监听器，发起请求的一个或多个主站和互连逻辑 耦合到一个或多个主器件和互连结构。 互连逻辑通过针对受保护资源的多个组中的任一个的请求的互连结构来调节到窥探者的传送速率。
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