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公开(公告)号：US08644759B2
公开(公告)日：2014-02-04
申请号：US12349011
申请日：2009-01-06
IPC分类号： H04B5/00
CPC分类号： H03F3/45179 , H03F1/0261 , H03F3/45475 , H03F3/45973 , H03F2200/534 , H03F2200/537 , H03F2200/54 , H03F2200/541 , H03F2203/45101 , H03F2203/45212 , H03F2203/45518 , H03F2203/45524 , H03F2203/45528 , H04B5/0031
摘要： Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.
摘要翻译： 在与输入到放大器的数据信号直流隔离的高性能放大器的输入上开发的浮动电压上的偏移电压通过在输入节点和预定电位之间连接高电阻元件而被消除，在邻近通信系统中特别有用，其中两个 芯片通过在两个芯片中共同形成的电容或电感耦合电路连接。 电阻元件可以是连接在节点和期望偏置电压之间的截止MOS晶体管，或者其栅极和漏极连接到电位的MOS晶体管。 可以将多个偏置电压分配给所有接收器，并由多路复用器本地选择以应用于接收器的一个或两个输入节点。 当电阻元件与数据速率相比具有长时间常数或电阻元件是非线性时，接收器输出也可以用作预定电位。
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92.发明授权Method for reducing power consumption by using capacitive coupling to perform majority detection 有权通过使用电容耦合来执行多数检测来降低功耗的方法公开(公告)号：US08472206B2
公开(公告)日：2013-06-25
申请号：US13235152
申请日：2011-09-16
申请人： Ronald Ho , Robert J. Drost , Robert Hopkins
发明人： Ronald Ho , Robert J. Drost , Robert Hopkins
CPC分类号： G06F1/189
摘要： One embodiment of the present invention provides a method that reduces power consumption by using capacitive coupling to perform a majority detection operation. The method involves driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. In addition, method involves feeding a signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The method further involves using the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by a computer system.
摘要翻译： 本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的方法。 该方法涉及将多个信号驱动到多个从动导线上。 然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。 此外，方法包括将多个检测线上的信号和偏置电压馈送到差分接收器。 如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。 该方法还包括使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。 优化信号传输减少了计算机系统消耗的功耗。
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公开(公告)号：US20120128037A1
公开(公告)日：2012-05-24
申请号：US12954474
申请日：2010-11-24
CPC分类号： H04B3/36
摘要： The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.
摘要翻译： 所公开的实施例提供异步操作的先入先出（FIFO）电路。 FIFO电路包括包含通过数据线段顺序连接的数据锁存器的数据路径。 FIFO电路还包括一个控制电路，该控制电路为数据锁存器产生控制信号，使得数据通路的行为类似于FIFO。 控制电路包括通过控制线段和位于控制线段内的中继器而相互连接的控制组件。 控制组件被配置为异步地生成用于数据锁存器的控制信号，并且中继器被配置为重复异步控制组件之间传送的异步信号。
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公开(公告)号：US20110302465A1
公开(公告)日：2011-12-08
申请号：US13212900
申请日：2011-08-18
IPC分类号： G06F11/07
CPC分类号： H04B5/0075 , H01L25/065 , H01L2924/0002 , H04B17/318 , H04L1/0009 , Y10T29/49133 , H01L2924/00
摘要： In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels.
摘要翻译： 在接近通信系统中，一个芯片上的发射元件与与第一芯片并置的第二芯片上的接收元件对齐。 然而，如果元件是静态的或动态的，则芯片之间的耦合会降低。 可以通过可控地降低系统的性能来补偿未对准。 例如，可以增加发射信号强度。 可以增加用于偏置每个位的位周期或时间段，从而降低带宽。 诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。 可以通过减少每个符号的比特数来增加诸如图像的符号的粒度。 诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。
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公开(公告)号：US08035436B2
公开(公告)日：2011-10-11
申请号：US12566506
申请日：2009-09-24
IPC分类号： H03H11/16
CPC分类号： H03D13/00
摘要： A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal.
摘要翻译： 描述了相位插值器电路。 在相位插值器电路中，基于第一参考信号和第二参考信号的加权求和产生具有基频和相位的输出信号，其中第一参考信号具有基频和第一相位 ，第二参考信号具有相同的基频和第二相位。 注意，基于相位插值器电路中的加权电路中的相关联的第一和第二阻抗值来确定第一参考信号和第二参考信号对输出信号的贡献。 例如，可以使用两个电容器的可编程电容比来在第一参考信号和第二参考信号之间进行内插。 另外，相位插值器电路可以包括向加权电路提供DC偏置并且放大加权电路的输出以提供输出信号的偏置电路。
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96.发明申请METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR CHIPS USING VARYING AREAS OF PRECISION 审中-公开使用精度变化区域制作半导体器件的方法和装置公开(公告)号：US20100244288A1
公开(公告)日：2010-09-30
申请号：US12813808
申请日：2010-06-11
申请人： David C. Douglas , Ronald Ho , Robert J. Drost
发明人： David C. Douglas , Ronald Ho , Robert J. Drost
IPC分类号： H01L23/544 , G03B27/52
CPC分类号： G03F7/70433
摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.
摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。
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97.发明授权Proximity optical memory module having an electrical-to-optical and optical-to-electrical converter 有权接近光学存储器模块，其具有电 - 光和光 - 电转换器公开(公告)号：US07786427B2
公开(公告)日：2010-08-31
申请号：US12115989
申请日：2008-05-06
IPC分类号： G01J1/04
CPC分类号： G11C5/04 , G11C5/143 , G11C7/1051 , G11C7/1054 , G11C7/1078 , G11C7/1081 , H01L23/48 , H01L23/642 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/167 , H01L2225/06562 , H01L2924/01067 , H01L2924/14 , H01L2924/19041
摘要： A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.
摘要翻译： 存储器模块由多个存储器芯片和固定在基板上的光学接口芯片形成。 芯片通过邻近通信（PxC）相互连接，其中每个芯片包括发射和接收元件，例如当芯片彼此面对放置在一起时形成电容耦合链路的电焊盘。 PxC链路可以直接在芯片之间或通过中间无源桥芯片。 接口芯片耦合到外部光通道并且包括用于与存储器芯片通信的光学和电信号之间的转换器，控制电路，缓冲器和PxC元件。 存储器阵列可以是形成冗余PxC网络的接口芯片周围的线性或二维阵列，可选地具有冗余PxC连接。 多个矩形存储器芯片可以将它们的窄边呈现给接口芯片以最大化带宽。
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98.发明授权Method and apparatus for refreshing receiver circuits using extra communication bits 有权使用额外的通信位刷新接收机电路的方法和装置公开(公告)号：US07715420B1
公开(公告)日：2010-05-11
申请号：US11651222
申请日：2007-01-05
申请人： Robert J. Drost , Ronald Ho
发明人： Robert J. Drost , Ronald Ho
IPC分类号： H04L12/28
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： One embodiment of the present invention provides a system that facilitates biasing receiver circuits within an integrated circuit. During operation, the system provides n receiver circuits within the integrated circuit to be biased. Next, the system provides n+m communication channels between n drivers and n receivers, wherein m is a number of additional communication channels, and wherein m>0. Then, the system couples the n+m communication channels to the n drivers, wherein each driver is selectively coupled to m+1 communication channels. The system also couples the n+m communication channels to the n receivers, wherein each receiver is selectively coupled to m+1 communication channels. In this way, at any given time n of the communication channels are active and m of the communication channels are inactive. Finally, the system refreshes inactive m communication channels' biases while the m inactive communication channels are not communicating signals.
摘要翻译： 本发明的一个实施例提供了一种便于在集成电路内偏置接收器电路的系统。 在运行期间，系统提供集成电路内的n个接收器电路以进行偏置。 接下来，该系统在n个驱动器和n个接收器之间提供n + m个通信信道，其中m是多个附加通信信道，并且其中m> 0。 然后，系统将n + m通信信道耦合到n个驱动器，其中每个驱动器选择性地耦合到m + 1个通信信道。 该系统还将n + m个通信信道耦合到n个接收机，其中每个接收机选择性地耦合到m + 1个通信信道。 以这种方式，在任何给定的时间，n个通信信道是有效的，并且通信信道的m是无效的。 最后，当m个无效通信信道不通信信号时，系统刷新无效的通信信道偏移。
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公开(公告)号：US07693424B1
公开(公告)日：2010-04-06
申请号：US11165917
申请日：2005-06-24
IPC分类号： H04B10/00
CPC分类号： G02B6/43 , G02B6/4204 , H01L25/0652 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A system that facilitates high-speed data transfer between integrated circuit chips. The system contains a first integrated circuit chip, which includes a capacitive receiver and an electrical-to-optical transceiver. The capacitive receiver receives a capacitively coupled voltage signal transmitted from a corresponding capacitive transmitter located on a second integrated circuit chip and converts the capacitively coupled voltage signal into an electrical signal. The electrical-to-optical transceiver converts the electrical signal to an optical signal and transmits the optical signal to an optical device through optical coupling.
摘要翻译： 一种促进集成电路芯片之间高速数据传输的系统。 该系统包含第一集成电路芯片，其包括电容接收器和电对光收发器。 电容式接收器接收从位于第二集成电路芯片上的对应的电容式发射机发送的电容耦合电压信号，并将电容耦合的电压信号转换为电信号。 电光收发器将电信号转换为光信号，并通过光耦合将光信号传输到光学装置。
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公开(公告)号：US20090322377A1
公开(公告)日：2009-12-31
申请号：US12163924
申请日：2008-06-27
IPC分类号： H01L25/00
CPC分类号： H04L47/30 , H04L47/10 , H04L49/90 , H04L49/9078
摘要： A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, wherein a size of the second buffer is defined by a distance of the second buffer from the input and the transfer rate of data, and wherein the distance between the first buffer and the input is different from the distance between the second buffer and the input.
摘要翻译： 一种包括第一缓冲器和第二缓冲器的系统，其中所述第一缓冲器和所述第二缓冲器连接到相同的输入，其中所述第一缓冲器的大小由所述第一缓冲器与所述输入端的距离定义， 的数据，其中所述第二缓冲器的大小由所述第二缓冲器与所述输入的距离和所述数据的传送速率定义，并且其中所述第一缓冲器和所述输入之间的距离不同于所述第二缓冲器和 输入。
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