公开(公告)号：US20140209898A1

公开(公告)日：2014-07-31

申请号：US14162364

申请日：2014-01-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiaki Yamamoto ,  Koichi Ito ,  Motomu Kurata ,  Taiga Muraoka ,  Daigo Ito

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: When an oxide semiconductor film is microfabricated to have an island shape, with the use of a hard mask, unevenness of an end portion of the oxide semiconductor film can be suppressed. Specifically, a hard mask is formed over the oxide semiconductor film, a resist is formed over the hard mask, light exposure is performed to form a resist mask, the hard mask is processed using the resist mask as a mask, the oxide semiconductor film is processed using the processed hard mask as a mask, the resist mask and the processed hard mask are removed, a source electrode and a drain electrode are formed in contact with the processed oxide semiconductor film, a gate insulating film is formed over the source electrode and the drain electrode, and a gate electrode is formed over the gate insulating film, the gate electrode overlapping with the oxide semiconductor film.

Abstract translation: 当氧化物半导体膜被微细化以具有岛状时，通过使用硬掩模，可以抑制氧化物半导体膜的端部的不均匀性。 具体地，在氧化物半导体膜上形成硬掩模，在硬掩模上形成抗蚀剂，进行曝光以形成抗蚀剂掩模，使用抗蚀剂掩模作为掩模来处理硬掩模，氧化物半导体膜为 使用处理后的硬掩模作为掩模处理，除去抗蚀剂掩模和加工的硬掩模，形成与处理的氧化物半导体膜接触的源电极和漏电极，在源极上形成栅极绝缘膜， 漏电极和栅电极形成在栅极绝缘膜上方，栅电极与氧化物半导体膜重叠。

公开(公告)号：US08748241B2

公开(公告)日：2014-06-10

申请号：US13716899

申请日：2012-12-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Yutaka Okazaki ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Motomu Kurata

IPC: H01L21/339 ,  H01L21/00 ,  H01L21/84 ,  H01L21/76

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。

公开(公告)号：US20140077205A1

公开(公告)日：2014-03-20

申请号：US14021618

申请日：2013-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Masashi Tsubuku

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/14616 ,  H01L27/14689 ,  H01L29/7869 ,  H01L29/78696

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

Abstract translation: 提高了晶体管的导通状态特性，因此提供了能够进行高速响应和高速操作的半导体器件。 制作出具有稳定电特性的高可靠性的半导体器件。 半导体器件包括：包括第一氧化物层的晶体管; 在所述第一氧化物层上的氧化物半导体层; 与氧化物半导体层接触的源电极层和漏电极层; 氧化物半导体层上的第二氧化物层; 第二氧化物层上的栅极绝缘层; 以及栅极绝缘层上的栅极电极层。 第二氧化物层的端部和栅极绝缘层的端部与源极电极层和漏极电极层重叠。