公开(公告)号：US09870730B2

公开(公告)日：2018-01-16

申请号：US14920596

申请日：2015-10-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Ji-Sun Kim ,  Jun Hyun Park ,  Young Wan Seo ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G3/36 ,  G09G3/20 ,  H03K19/0175

CPC classification number: G09G3/2092 ,  G09G2310/0286 ,  H03K19/017509

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

公开(公告)号：US09647079B2

公开(公告)日：2017-05-09

申请号：US15069239

申请日：2016-03-14

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun Park ,  Kyoung Ju Shin

IPC: H01L33/00 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/42384 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L2029/42388

Abstract: Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor.

公开(公告)号：US20170069282A1

公开(公告)日：2017-03-09

申请号：US15135425

申请日：2016-04-21

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun Park ,  Keum Nam Kim ,  Sung Hwan Kim ,  Kyoung Ju Shin

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2230/00 ,  G09G2310/0216 ,  G09G2310/0224 ,  G09G2310/0251 ,  G09G2310/0286 ,  G11C19/287

Abstract: A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.

Abstract translation: 扫描驱动器包括被配置为向扫描线提供扫描信号的多个级。 在面板一侧的第i（i是自然数）阶段包括：连接在第一输入端和第一节点之间的第一晶体管，并且包括连接到第二输入端的栅电极; 连接在第三输入端子和第一输出端子之间的第二晶体管，用于输出扫描信号的第i扫描信号，并且包括连接到第一节点的栅电极; 连接在第一输出端子和被配置为接收第一截止电压的第一电力输入端子之间的第三晶体管，并且包括连接到第二输入端子的栅电极; 以及连接在第一节点和第一输出端子之间的第一电容器。