摘要:
A caster assembly for a frame is described that permits a frame to be easily moved and placed. The caster assembly, which may lift a leg of the frame, can be placed or removed without picking up the frame. The caster assembly further includes a handle that moves a cam for engaging the caster assembly with the leg. A frame having at least one caster assembly is also described.
摘要:
Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.
摘要:
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.
摘要:
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要:
The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.
摘要:
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要:
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes.
摘要:
Provided is a apparatus for testing reliability of a semiconductor sample including: a sample mounting part for mounting the semiconductor sample on an upper center part thereof, and mounting components having an evaluation circuit board at an upper peripheral part thereof; a heating block formed to have a tip shape and mounted on a lower part of the semiconductor sample to maintain a test temperature; a cooling block separated from the heating block and surrounding the heating block to cool the temperature of the components; and a fixing block for raising and lowering the semiconductor sample.
摘要:
A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.
摘要:
Non-activated tissue-regeneration polypeptides (TRPs) and their preparation methods are disclosed. The TRPs include: a protein transduction domain (PTD) making the polypeptides to permeate a cell membrane without cell membrane receptors; a furin activation domain (FAD) which has at least one proprotein convertase cleavage site and which can be cleaved by the proprotein convertase and activate a tissue regeneration domain (TRD) in cells; and a tissue regeneration domain (TRD) which can be activated by the proprotein convertase cleavage of the FAD to stimulate the growth or formation of tissues or to induce the regeneration of tissues. The TRPs can be mass-produced by cultured bacteria, such as recombinant E. coli, are in a non-activated state before in vivo administration, and their separation, purification, handling, storage and administration are simple and convenient. The in vivo administration of the TRPs is useful to stimulate the formation or regeneration of tissues, such as bones or cartilages, or to improve the fibrosis and cirrhosis of organs, such as kidneys, liver, lungs and heart by pharmacological mechanisms completely different from those of prior rhBMPs or TGF-β proteins.