公开(公告)号：US08143935B2

公开(公告)日：2012-03-27

申请号：US11881816

申请日：2007-07-26

申请人： Alexander Dribinsky ,  Tae Youn Kim ,  Dylan J. Kelly ,  Christopher N. Brindle

发明人： Alexander Dribinsky ,  Tae Youn Kim ,  Dylan J. Kelly ,  Christopher N. Brindle

IPC分类号： H03K17/00

摘要： A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

公开(公告)号：US20070069291A1

公开(公告)日：2007-03-29

申请号：US11520912

申请日：2006-09-14

申请人： Michael Stuber ,  Christopher Brindle ,  Dylan Kelly ,  Clint Kemerling ,  George Imthurn ,  Robert Welstand ,  Mark Burgener ,  Alexander Dribinsky ,  Tae Kim

发明人： Michael Stuber ,  Christopher Brindle ,  Dylan Kelly ,  Clint Kemerling ,  George Imthurn ,  Robert Welstand ,  Mark Burgener ,  Alexander Dribinsky ,  Tae Kim

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化物可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

公开(公告)号：US08954902B2

公开(公告)日：2015-02-10

申请号：US13028144

申请日：2011-02-15

申请人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

发明人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

IPC分类号： G06F17/50 ,  H03K17/16 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

公开(公告)号：US07671643B2

公开(公告)日：2010-03-02

申请号：US12006467

申请日：2008-01-03

申请人： Alexander Dribinsky ,  Gregory Pucci

发明人： Alexander Dribinsky ,  Gregory Pucci

IPC分类号： H03L7/00

CPC分类号： H03K17/22 ,  H03K2217/0036

摘要： A power-on-reset (POR) circuit having a zero or substantially zero current state while the supply voltage is in a predetermined, valid range is disclosed. The POR circuit includes a state machine, an oscillator, and output circuitry that are electrically coupled to one another and to a supply voltage. Output from the output circuitry is also provided to the integrated circuit to which the POR circuit is coupled. The state machine includes a plurality of sequential circuits such as latches, flip-flops, and the like that are electrically coupled in a cascade, to provide a ripple counter. The output circuitry is structured and arranged to reset or initialize all of the logic elements on the chip by generating a POR output logic HI (1) signal by Boolean operation of the logic circuitry signal of the state machine for all Boolean states except one. The oscillator is disabled when the POR output logic signal is LO (0), which causes the POR circuit to enter a zero or substantially zero current state.

摘要翻译： 公开了一种在电源电压处于预定的有效范围内具有零或基本零电流状态的上电复位（POR）电路。 POR电路包括电耦合到电源电压的状态机，振荡器和输出电路。 输出电路的输出也提供给POR电路耦合到的集成电路。 状态机包括串联电耦合的多个时序电路，例如锁存器，触发器等，以提供纹波计数器。 输出电路被构造和布置成通过对除了一个之外的所有布尔状态的状态机的逻辑电路信号的布尔运算产生POR输出逻辑HI（1）信号来复位或初始化芯片上的所有逻辑元件。 当POR输出逻辑信号为LO（0）时，振荡器被禁止，这导致POR电路进入零或基本零电流状态。

公开(公告)号：US20050274180A1

公开(公告)日：2005-12-15

申请号：US11146993

申请日：2005-06-07

申请人： Yang Zhao ,  Albert Leung ,  Michael Rebeschini ,  Gregory Pucci ,  Alexander Dribinsky ,  Yongyao Cai

发明人： Yang Zhao ,  Albert Leung ,  Michael Rebeschini ,  Gregory Pucci ,  Alexander Dribinsky ,  Yongyao Cai

IPC分类号： G01P15/00

CPC分类号： G01P15/008

摘要： A thermal accelerometer device that provides a compensation for sensitivity variations over temperature. The thermal accelerometer includes signal conditioning circuitry operative to receive analog signals representing a differential temperature is indicative of a sensed acceleration. The signal conditioning circuitry includes serially connected A-to-D and D-to-A converters, which implement a temperature dependent function and process the received signals to provide a compensation for sensitivity variations over a range of ambient temperature. To provide a ratiometric compensation for variations in power supply voltage, a buffered voltage proportional to the supply voltage is provided as a reference voltage to the D-to-A converter. The thermal accelerometer includes a self-test circuit for verifying the integrity of a heater, temperature sensors, and circuitry included within the device.

摘要翻译： 一种热敏加速度计装置，可提供对温度敏感度变化的补偿。 热加速度计包括信号调节电路，其操作以接收表示差分温度的模拟信号，其指示感测到的加速度。 信号调理电路包括串行连接的A到D和D到A转换器，其实现温度依赖功能并处理接收到的信号以提供在环境温度范围内的灵敏度变化的补偿。 为了提供电源电压变化的比例补偿，将与电源电压成比例的缓冲电压作为参考电压提供给D转换器。 热加速度计包括用于验证加热器，温度传感器和包括在装置内的电路的完整性的自检电路。

公开(公告)号：US06795752B1

公开(公告)日：2004-09-21

申请号：US09705996

申请日：2000-11-03

申请人： Yang Zhao ,  Adrian Paul Brokaw ,  Michael E. Rebeschini ,  Albert M. Leung ,  Gregory P. Pucci ,  Alexander Dribinsky

发明人： Yang Zhao ,  Adrian Paul Brokaw ,  Michael E. Rebeschini ,  Albert M. Leung ,  Gregory P. Pucci ,  Alexander Dribinsky

IPC分类号： G01P1500

CPC分类号： G01P15/008 ,  G01P15/08 ,  G01P15/12

摘要： An integrated convective accelerometer device. The device includes a thermal acceleration sensor having a thermopile and a heater element; control circuitry for providing closed-loop control of the thermopile common-mode voltage; an instrumentation amplifier; clock generation circuitry; voltage reference circuitry; a temperature sensor; and, output amplifiers. The device can be operated in an absolute or ratiometric mode. Further, the device is formed in a silicon substrate using standard semiconductor processes and is packaged in a standard integrated circuit package.

摘要翻译： 一体化对流加速度计装置。 该装置包括具有热电堆和加热元件的热​​加速度传感器; 用于提供热电堆共模电压的闭环控制的控制电路; 仪表放大器; 时钟发生电路; 电压参考电路; 温度传感器; 和输出放大器。 该设备可以以绝对或比例模式运行。 此外，使用标准半导体工艺在硅衬底中形成器件，并封装在标准集成电路封装中。

公开(公告)号：US20110227637A1

公开(公告)日：2011-09-22

申请号：US13028144

申请日：2011-02-15

申请人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

发明人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

IPC分类号： G05F1/10 ,  H01L29/772

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

公开(公告)号：US07890891B2

公开(公告)日：2011-02-15

申请号：US11520912

申请日：2006-09-14

申请人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Robert B. Welstand ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

发明人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Robert B. Welstand ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

IPC分类号： G06F17/50

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

公开(公告)号：US20080076371A1

公开(公告)日：2008-03-27

申请号：US11881816

申请日：2007-07-26

申请人： Alexander Dribinsky ,  Tae Kim ,  Dylan Kelly ,  Christopher Brindle

发明人： Alexander Dribinsky ,  Tae Kim ,  Dylan Kelly ,  Christopher Brindle

IPC分类号： H04B1/16

CPC分类号： H03K17/161 ,  H03K17/04 ,  H03K17/06 ,  H03K17/08 ,  H03K17/102 ,  H03K17/284 ,  H03K17/6874 ,  H03K17/689 ,  H03K2217/0009

摘要： A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

摘要翻译： 公开了一种用于控制电路中的电荷注入的电路和方法。 在一个实施例中，电路和方法用于绝缘体上半导体（SOI）射频（RF）开关中。 在一个实施例中，SOI RF开关包括串联耦合的多个开关晶体管，被称为“堆叠”晶体管，并且在SOI衬底上被实现为单片集成电路。 电荷注入控制元件被耦合以从位于开关晶体管之间的电阻隔离节点接收注入的电荷，并且将注入的电荷传送到不被电阻隔离的至少一个节点。 在一个实施例中，电荷注入控制元件包括电阻器。 在另一个实施例中，电荷注入控制元件包括晶体管。 公开了一种用于控制开关电路中的电荷注入的方法，其中注入的电荷在串联耦合的开关晶体管之间的电阻隔离节点处产生，并且注入的电荷被传送到不被电阻隔离的开关电路的至少一个节点。

公开(公告)号：US5999115A

公开(公告)日：1999-12-07

申请号：US63242

申请日：1998-04-20

申请人： Lawrence E. Connell ,  Alexander Dribinsky

发明人： Lawrence E. Connell ,  Alexander Dribinsky

IPC分类号： H03M1/68 ,  H03M1/76

CPC分类号： H03M1/687 ,  H03M1/76 ,  H03M1/765

摘要： A digital-to-analog converter with cascaded coarse and fine resistor divider strings. The fine resistor string contains 2.sup.N or more resistor segments controlled by N number of fine divider control bits. Resistors located at each end of the fine divider string are a fraction of the nominal value for the remaining fine divider resistor segments. The on-resistance of switches coupling the coarse and fine resistor divider strings is less than or equal to a predetermined fraction of the nominal value for the fine divider resistor segments to minimize contributions to linearity error. The DAC uses all CMOS devices including NMOS and PMOS switches which utilize approximately the full rail-to-rail voltage of the voltage source without the use of additional amplifiers. The DAC provides linearity of about one-fourth LSB.

摘要翻译： 具有级联粗细和精细电阻分压器串的数模转换器。 精细电阻串包含2N个或更多个由N个分频器控制位控制的电阻段。 位于精细分压器串的每一端的电阻器是剩余精细分压电阻器段的标称值的一小部分。 耦合粗电阻和精细电阻分压器串的开关的导通电阻小于或等于精细分压电阻器段的额定值的预定分数，以使对线性误差的贡献最小化。 DAC使用所有CMOS器件，包括NMOS和PMOS开关，其利用大约电压源的完全轨到轨电压，而不使用额外的放大器。 DAC提供大约四分之一LSB的线性度。