公开(公告)号：US07782112B2

公开(公告)日：2010-08-24

申请号：US12330947

申请日：2008-12-09

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Akinori Matsumoto

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Akinori Matsumoto

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  H03K5/1565 ,  H03K23/54 ,  H03K2005/00241

摘要： In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.

摘要翻译： 在用于从输入多相时钟信号产生期望相位的时钟信号的装置中，中间时钟发生器通过使用输入多相时钟信号之一作为参考时钟信号来产生多相中间时钟信号 哪个周期等于参考时钟信号的多个周期。 第一相位选择器选择多相中间时钟信号之一。 第二相位选择器选择多相时钟信号之一。 锁存电路将由第一相位选择器选择的中间时钟信号与由第二相位选择器选择的时钟信号进行锁存。

公开(公告)号：US20090278614A1

公开(公告)日：2009-11-12

申请号：US12096664

申请日：2006-10-25

申请人： Shiro Dosho ,  Kazuaki Sogawa ,  Yuji Yamada ,  Naoshi Yanagisawa

发明人： Shiro Dosho ,  Kazuaki Sogawa ,  Yuji Yamada ,  Naoshi Yanagisawa

IPC分类号： H03L7/08

CPC分类号： H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/107 ,  H03L7/183 ,  H03L2207/06

摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).

摘要翻译： 常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益 ），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。 电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益 确定单元（90）。

公开(公告)号：US20080303567A1

公开(公告)日：2008-12-11

申请号：US12033707

申请日：2008-02-19

申请人： Shiro SAKIYAMA ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro SAKIYAMA ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US20070205825A1

公开(公告)日：2007-09-06

申请号：US10594398

申请日：2004-11-17

申请人： Shiro Dosho ,  Yusuke Tokunaga

发明人： Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03K5/00

CPC分类号： H03L7/093 ,  H03H19/004 ,  H03L7/0891

摘要： A loop filter (30) includes a first capacitor (31) provided between an input terminal for a current signal and a reference voltage, a switched capacitor circuit (32) provided between the input terminal and the first capacitor (31) and a second capacitor (33) provided in parallel to the first capacitor (31) and the switched capacitor circuit (32). In the switched capacitor circuit (32), when a third capacitor (321) is connected to the first capacitor (31), a fourth capacitor (322) is connected to the second capacitor (33). In the loop filter (30) having the above-described configuration, a capacitance value of the second capacitor (33) is set to be larger than respective capacitance values of the third and fourth capacitors (321 and 322).

摘要翻译： 环路滤波器（30）包括设置在电流信号的输入端和参考电压之间的第一电容器（31），设置在输入端和第一电容器（31）之间的开关电容电路（32）和第二电容器 （33）与所述第一电容器（31）和所述开关电容器电路（32）并联设置。 在开关电容电路（32）中，当第三电容器（321）连接到第一电容器（31）时，第四电容器（322）连接到第二电容器（33）。 在具有上述结构的环路滤波器（30）中，第二电容器（33）的电容值被设定为大于第三和第四电容器（321和322）的各个电容值。

公开(公告)号：US20070096961A1

公开(公告)日：2007-05-03

申请号：US10580842

申请日：2004-10-14

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Shiro Dosho

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Shiro Dosho

IPC分类号： H03M7/30

CPC分类号： G10L21/04

摘要： In a signal processing device which performs data compression, a thinning circuit 1 generates thinned data by thinning input PCM data. For example, when a sampling rate fs of the PCM data (original data) is fs=10 Hz, thinned data of fs=1 Hz is generated. The determination circuit 2 controls the selection circuit 4 so that, based on the following expression: TOTAL1=|X(n)−X(n−1)|+|X(n−1)−X(n−2)|+ . . . +|X(n−8)−X(n−9)| if TOTAL1>C1, the input PCM data is selected, and if otherwise the thinned data is selected. The selected data and the determination result information of the determination circuit 2 are written into a memory 3. Therefore, data compression is performed with respect to original data with a simple circuit configuration and without losing required information of the original data.

摘要翻译： 在执行数据压缩的信号处理装置中，细化电路1通过稀释输入PCM数据来生成稀疏数据。 例如，当PCM数据（原始数据）的采样率fs为fs = 10Hz时，产生fs = 1Hz的稀疏数据。 确定电路2控制选择电路4，使得基于以下表达式：<？in-line-formula description =“In-line formula”end =“lead”？> TOTAL1 = | X（n）-X（ n-1）| + | X（n-1）-X（n-2）| +。 。 。 + | X（n-8）-X（n-9）| <？in-line-formula description =“内联公式”end =“tail”？>如果TOTAL 1> C 1，输入的PCM数据 选择，如果否则选择了稀疏数据。 所选择的数据和确定电路2的确定结果信息被写入存储器3。 因此，利用简单的电路配置对原始数据执行数据压缩，并且不丢失原始数据的所需信息。

公开(公告)号：US20070090859A1

公开(公告)日：2007-04-26

申请号：US11513239

申请日：2006-08-31

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03K19/094

CPC分类号： H03K19/018571 ,  H03F1/0261 ,  H03F3/505 ,  H03F2200/18 ,  H04L25/028

摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

摘要翻译： 源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。 因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。 因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器 使用输入数据信号从低电平变为高电平时的一个时钟周期。 两个来源追随者在适当的时机运行。

公开(公告)号：US20060181491A1

公开(公告)日：2006-08-17

申请号：US11401399

申请日：2006-04-11

申请人： Yoshito Date ,  Tetsuro Omori ,  Shiro Dosho ,  Makoto Mizuki

发明人： Yoshito Date ,  Tetsuro Omori ,  Shiro Dosho ,  Makoto Mizuki

IPC分类号： G09G3/30

CPC分类号： G09G3/3283 ,  G09G3/3241 ,  G09G2310/027 ,  G09G2320/0233 ,  G09G2330/028

摘要： The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.

摘要翻译： 第一和第二芯片并排设置。 第一芯片包括：电流供应部分，用于输出驱动电流;电流供应部分包括电流镜; 电流分布MISFET; 电流输入MISFET，用于将电流传输到电流供应部分，电流输入MISFET连接到电流分布MISFET; 和第二电流分布MISFET。 电流分布MISFET和第二电流分布MISFET构成电流镜。 第二芯片包括连接到第二电流分布MISFET的第二电流输入MISFET。 电流分布MISFET的W / L比与与其连接的电流输入MISFET的W / L比之间的比率在第一和第二芯片中是相同的。

公开(公告)号：US20060097772A1

公开(公告)日：2006-05-11

申请号：US11188855

申请日：2005-07-26

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

公开(公告)号：US20050174145A1

公开(公告)日：2005-08-11

申请号：US10513965

申请日：2003-08-27

申请人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

发明人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

IPC分类号： G09G3/36 ,  H04L25/02 ,  H04L25/49 ,  H03K19/094

CPC分类号： G09G3/3685 ,  G09G2310/027 ,  G09G2330/06 ,  H04L25/0272 ,  H04L25/4902

摘要： In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

摘要翻译： 在传送与时钟信号同步的时钟信号和多个数据信号的过程中，驱动器开关的驱动脉冲宽度被时钟传输系统（12）反馈控制，从而传输时钟信号 在一个小幅度。 具有脉冲宽度的控制信号用于控制每个数据传输系统（13）中的驱动器开关，从而同时实现以小幅度传送每个数据信号。 此外，在时钟接收系统（10）中，具有脉冲宽度的控制信号用于时钟延迟电路的延迟控制，从而实现每个数据接收系统（11）中的接收数据的最佳锁存定时。

公开(公告)号：US06528982B1

公开(公告)日：2003-03-04

申请号：US09697721

申请日：2000-10-27

申请人： Naoshi Yanagisawa ,  Shiro Dosho ,  Kazuhiko Nishikawa ,  Seiji Watanabe ,  Takahiro Bokui

发明人： Naoshi Yanagisawa ,  Shiro Dosho ,  Kazuhiko Nishikawa ,  Seiji Watanabe ,  Takahiro Bokui

IPC分类号： G01R2500

CPC分类号： G01R25/00

摘要： A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. The comparison pulse generator outputs one phase difference comparison pulse after another. Each phase difference comparison pulse has a width representing the phase difference between first and second input signals. The periodic signal generator outputs a periodic signal every time a value obtained by accumulating the widths of the phase difference comparison pulses exceeds a predetermined value. Receiving the periodic signal and a clock signal with a period shorter than that of the periodic signal, the counter counts the number of pulses of the clock signal during one period of the periodic signal and outputs a resultant count. And the arithmetic unit detects and outputs a variation in the count as jitter between the first and second input signals.

摘要翻译： 抖动检测器获得输入信号之间的相位差作为数字值，使信号之间的抖动容易检测。 抖动检测器包括比较脉冲发生器，周期信号发生器，计数器和算术单元。 比较脉冲发生器输出一个相差差值比较脉冲。 每个相位差比较脉冲具有表示第一和第二输入信号之间的相位差的宽度。 每当通过累加相位差比较脉冲的宽度获得的值超过预定值时，周期性信号发生器输出周期信号。 接收到周期信号和周期信号的周期信号的时钟信号，计数器在周期信号的一个周期内对时钟信号的脉冲数进行计数，并输出结果计数。 并且算术单元检测并输出计数的变化，作为第一和第二输入信号之间的抖动。