公开(公告)号：US20070096961A1

公开(公告)日：2007-05-03

申请号：US10580842

申请日：2004-10-14

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Shiro Dosho

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Shiro Dosho

IPC分类号： H03M7/30

CPC分类号： G10L21/04

摘要： In a signal processing device which performs data compression, a thinning circuit 1 generates thinned data by thinning input PCM data. For example, when a sampling rate fs of the PCM data (original data) is fs=10 Hz, thinned data of fs=1 Hz is generated. The determination circuit 2 controls the selection circuit 4 so that, based on the following expression: TOTAL1=|X(n)−X(n−1)|+|X(n−1)−X(n−2)|+ . . . +|X(n−8)−X(n−9)| if TOTAL1>C1, the input PCM data is selected, and if otherwise the thinned data is selected. The selected data and the determination result information of the determination circuit 2 are written into a memory 3. Therefore, data compression is performed with respect to original data with a simple circuit configuration and without losing required information of the original data.

摘要翻译： 在执行数据压缩的信号处理装置中，细化电路1通过稀释输入PCM数据来生成稀疏数据。 例如，当PCM数据（原始数据）的采样率fs为fs = 10Hz时，产生fs = 1Hz的稀疏数据。 确定电路2控制选择电路4，使得基于以下表达式：<？in-line-formula description =“In-line formula”end =“lead”？> TOTAL1 = | X（n）-X（ n-1）| + | X（n-1）-X（n-2）| +。 。 。 + | X（n-8）-X（n-9）| <？in-line-formula description =“内联公式”end =“tail”？>如果TOTAL 1> C 1，输入的PCM数据 选择，如果否则选择了稀疏数据。 所选择的数据和确定电路2的确定结果信息被写入存储器3。 因此，利用简单的电路配置对原始数据执行数据压缩，并且不丢失原始数据的所需信息。

公开(公告)号：US06833626B2

公开(公告)日：2004-12-21

申请号：US10189549

申请日：2002-07-08

申请人： Jun Kajiwara ,  Masayoshi Kinoshita ,  Shiro Sakiyama

发明人： Jun Kajiwara ,  Masayoshi Kinoshita ,  Shiro Sakiyama

IPC分类号： H01L2940

CPC分类号： H01L25/16 ,  G01R31/2853 ,  G01R31/318513 ,  H01L27/10897 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/3011 ,  H01L2224/05599

摘要： A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

摘要翻译： 大芯片包括从第一干线导线分支并延伸到相应导线的第一组支线，以便连接到相应的接合焊盘。 第一组的每条分支线包括连接控制元件和电阻器。 小芯片包括从第二干线分支的第二组支线，并延伸到相应的导线，以便连接到相应的接合焊盘。 第二组的每条分支线包括连接控制元件和电阻器。 通过在对第一和第二测试焊盘施加电压时测量电流值来确定接合焊盘之间是否正确地进行连接。

公开(公告)号：US20070132505A1

公开(公告)日：2007-06-14

申请号：US10588191

申请日：2005-02-14

申请人： Masayoshi Kinoshita ,  Shiro Sakiyama

发明人： Masayoshi Kinoshita ,  Shiro Sakiyama

IPC分类号： G05F1/10

CPC分类号： G05F3/30 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/153 ,  H03F2203/45136

摘要： In a reference voltage generation circuit, a bandgap reference circuit (BGR circuit) 1 includes diode element D1 and D2 having different current densities, three resistive elements R1, R2 and R3, a P-type first transistor Tr1 for supplying a current to a reference voltage output terminal O, a P-type second transistor Tr2 for determining a drain current flowing through the first transistor Tr1 by a current mirror structure, and a feedback type control circuit 11. The BGR circuit 1 is connected to a pull-down circuit 2. The pull-down circuit 2 includes a resistive element R4 and a P-type transistor Tr4 which are connected in series. The resistive element R4 is connected to a drain terminal of the second P-type transistor Tr2. The P-type transistor Tr4 has a gate terminal connected to the reference voltage output terminal O and a grounded drain terminal. Thus, the number of elements and current consumption in the start-up circuit which shifts the operation from an abnormal stabilization point to a normal stabilization point are reduced.

摘要翻译： 在参考电压产生电路中，带隙基准电路（BGR电路）1包括具有不同电流密度的二极管元件D 1和D 2，三个电阻元件R 1，R 2和R 3，P型第一晶体管Tr 1 向参考电压输出端子O提供电流，用于通过电流镜结构确定流过第一晶体管Tr 1的漏极电流的P型第二晶体管Tr 2和反馈型控制电路11。 BGR电路1连接到下拉电路2。 下拉电路2包括串联连接的电阻元件R 4和P型晶体管Tr 4。 电阻元件R 4连接到第二P型晶体管Tr 2的漏极端子。 P型晶体管Tr 4具有连接到参考电压输出端子O的栅极端子和接地漏极端子。 因此，将操作从异常稳定点转移到正常稳定点的起动电路中的元件数量和电流消耗减少。

公开(公告)号：US20050162212A1

公开(公告)日：2005-07-28

申请号：US10511165

申请日：2003-02-19

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Masaya Sumita

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Masaya Sumita

IPC分类号： G05F1/565 ,  H03K19/003 ,  H03K3/01

CPC分类号： G05F1/565 ,  H03K19/00384

摘要： In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.

摘要翻译： 在本发明的半导体集成电路中，主电路2包括源极和基板彼此分离的MOS晶体管。 基板电位控制电路1控制主电路2的MOS晶体管的基板电位，使得主电路2的MOS晶体管的实际饱和电流值等于工作电源电压下的目标饱和电流值Ids 主电路的Vdd 2。 因此，即使减小半导体集成电路的工作电源电压，也可以抑制操作速度的变化。

公开(公告)号：US20090115502A1

公开(公告)日：2009-05-07

申请号：US12093393

申请日：2007-09-04

申请人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Masayoshi Kinoshita

发明人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Masayoshi Kinoshita

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.

摘要翻译： 电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。 同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。 从电流镜电路10输出的两个电流分别分配给两个。 在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。 因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。 这轻而易举地减少了四分之一的必要阻力。

公开(公告)号：US07495504B2

公开(公告)日：2009-02-24

申请号：US10588191

申请日：2005-02-14

申请人： Masayoshi Kinoshita ,  Shiro Sakiyama

发明人： Masayoshi Kinoshita ,  Shiro Sakiyama

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F3/30 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/153 ,  H03F2203/45136

摘要： In a reference voltage generation circuit, a bandgap reference circuit (BGR circuit) 1 includes diode element D1 and D2 having different current densities, three resistive elements R1, R2 and R3, a P-type first transistor Tr1 for supplying a current to a reference voltage output terminal O, a P-type second transistor Tr2 for determining a drain current flowing through the first transistor Tr1 by a current mirror structure, and a feedback type control circuit 11. The BGR circuit 1 is connected to a pull-down circuit 2. The pull-down circuit 2 includes a resistive element R4 and a P-type transistor Tr4 which are connected in series. The resistive element R4 is connected to a drain terminal of the second P-type transistor Tr2. The P-type transistor Tr4 has a gate terminal connected to the reference voltage output terminal O and a grounded drain terminal. Thus, the number of elements and current consumption in the start-up circuit which shifts the operation from an abnormal stabilization point to a normal stabilization point are reduced.

摘要翻译： 在参考电压产生电路中，带隙参考电路（BGR电路）1包括具有不同电流密度的二极管元件D1和D2，三个电阻元件R1，R2和R3，用于向参考电压提供电流的P型第一晶体管Tr1 电压输出端子O，用于通过电流镜结构确定流过第一晶体管Tr1的漏极电流的P型第二晶体管Tr2和反馈型控制电路11.BGR电路1连接到下拉电路2 下拉电路2包括串联连接的电阻元件R4和P型晶体管Tr4。 电阻元件R4连接到第二P型晶体管Tr2的漏极端子。 P型晶体管Tr4具有连接到参考电压输出端子O的栅极端子和接地漏极端子。 因此，将操作从异常稳定点转移到正常稳定点的起动电路中的元件数量和电流消耗减少。

公开(公告)号：US06914259B2

公开(公告)日：2005-07-05

申请号：US10262669

申请日：2002-10-02

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Jun Kajiwara

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Jun Kajiwara

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/822 ,  H01L23/52 ,  H01L25/18 ,  H01L27/04 ,  H01L23/58

CPC分类号： G11C29/022 ,  G01R31/2853 ,  G01R31/318505 ,  G01R31/318513 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599

摘要： A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.

摘要翻译： 通过经由多个导电连接构件连接设置在例如两个半导体芯片上的多个连接焊盘来实现多芯片模块。 为了进行用于确定两个半导体芯片之间的连接质量的测试，多芯片模块还设置有多个开关元件，使得多个连接构件可以经由连接以串联方式导电 半导体芯片的焊盘。 在连接测试期间，所有的开关元件都被接通，并且使用两个探测器来测量包括以串行方式传导的多个连接构件的线的两端之间的阻抗。

公开(公告)号：US06429633B1

公开(公告)日：2002-08-06

申请号：US09530267

申请日：2000-04-28

申请人： Jun Kajiwara ,  Katsuji Satomi ,  Shiro Sakiyama ,  Masayoshi Kinoshita ,  Katsuhiro Ootani

发明人： Jun Kajiwara ,  Katsuji Satomi ,  Shiro Sakiyama ,  Masayoshi Kinoshita ,  Katsuhiro Ootani

IPC分类号： G05F140

CPC分类号： H03K17/164

摘要： In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.

摘要翻译： 在开关稳压器中，开关噪声降低，保持高的转换效率。 开关调节器包括具有不同导通电阻的多个输出开关晶体管21至23，它们在接通操作中工作时导通电阻的下降顺序，并且在关断操作中以导通电阻的升序操作。 以这种方式，可以在开关操作中抑制突然的电流变化，从而减少从寄生电感器102得到的di / dt噪声。

公开(公告)号：US06307360B1

公开(公告)日：2001-10-23

申请号：US09673851

申请日：2000-10-23

申请人： Jun Kajiwara ,  Shiro Sakiyama ,  Masayoshi Kinoshita ,  Katsuji Satomi ,  Katsuhiro Ootani

发明人： Jun Kajiwara ,  Shiro Sakiyama ,  Masayoshi Kinoshita ,  Katsuji Satomi ,  Katsuhiro Ootani

IPC分类号： G05F1563

CPC分类号： H02M1/36 ,  H02M1/32 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

摘要： The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.

摘要翻译： 同步整流模式的开关调节器包括串联布置在电源Vdd和接地Vss之间的第一和第二开关SW1，SW2，开关控制单元1，其控制开关SW1，SW2的开关操作，以及 平滑电路4，其平滑输出节点电位Vnd。 当信号Sc1表示输出节点电位Vnd低于第一基准电位Vr1时，第一参考电位Vr1是第一开关SW1处于导通状态时检测涌流的发生的基准，控制电路10关闭第一开关 SW1。 因此，通过利用由于第一开关SW1的导通电阻引起的电压降来进行浪涌电流的检测，从而不需要提供用于检测浪涌电流的电阻元件。

公开(公告)号：US20050116765A1

公开(公告)日：2005-06-02

申请号：US10994552

申请日：2004-11-23

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Masaya Sumita

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Masaya Sumita

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H03K5/00 ,  H03K5/13 ,  H03K19/00 ,  H03K19/094 ,  H03K3/037

CPC分类号： H03K5/133 ,  H03K19/0013 ,  H03K2005/00026 ,  H03K2005/00039 ,  H03K2005/00143 ,  H03K2005/00202

摘要： In a semiconductor integrated circuit, respective semiconductor circuits are disposed in different regions partitioned in accordance with their operation probabilities per unit time, and a supply voltage and a threshold voltage are correlatively controlled in each region. A target value for controlling the threshold voltage is determined in accordance with the operation probability of the semiconductor circuit. A threshold voltage control circuit controls substrate voltages of p-type and n-type MOS transistors included in the semiconductor circuit so that the threshold voltage can be constant at the target value regardless of the temperature change occurring in use. Simultaneously, a supply voltage control circuit controls the supply voltage for the semiconductor circuit so that an objective operating frequency can be attained. As a result, a semiconductor integrated circuit with low power consumption can be obtained.

摘要翻译： 在半导体集成电路中，将各个半导体电路设置在根据其每单位时间的操作概率分割的不同区域中，并且在每个区域中相关地控制电源电压和阈值电压。 根据半导体电路的运行概率来确定用于控制阈值电压的目标值。 阈值电压控制电路控制包括在半导体电路中的p型和n型MOS晶体管的衬底电压，使得阈值电压可以恒定在目标值，而与使用中发生的温度变化无关。 同时，电源电压控制电路控制半导体电路的电源电压，从而可以实现目标工作频率。 结果，可以获得具有低功耗的半导体集成电路。