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    Delay locked loop circuit
    1.
    发明申请
    Delay locked loop circuit 审中-公开
    延时锁定回路电路

    公开(公告)号：US20060176091A1

    公开(公告)日：2006-08-10

    申请号：US11289753

    申请日：2005-11-30

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

    摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

    摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

    Delay locked loop circuit
    2.
    发明授权
    Delay locked loop circuit 有权
    延时锁定回路电路

    公开(公告)号：US07705645B2

    公开(公告)日：2010-04-27

    申请号：US12033707

    申请日：2008-02-19

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

    摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

    摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延迟到参考时钟信号的下降（或上升）的间隔期间。

    DELAY LOCKED LOOP CIRCUIT
    3.
    发明申请
    DELAY LOCKED LOOP CIRCUIT 有权
    延迟锁定环路

    公开(公告)号：US20080303567A1

    公开(公告)日：2008-12-11

    申请号：US12033707

    申请日：2008-02-19

    申请人： Shiro SAKIYAMA ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

    发明人： Shiro SAKIYAMA ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

    摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

    摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

    Charge pumping circuit
    4.
    发明授权
    Charge pumping circuit 有权
    充电泵电路

    公开(公告)号：US07453313B2

    公开(公告)日：2008-11-18

    申请号：US11637687

    申请日：2006-12-13

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    IPC分类号： G06F3/02

    CPC分类号： H02M3/07 ,  H03L7/0895 ,  H03L7/0896

    摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

    摘要翻译： 电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。 推挽操作中的另一个用电流镜电路的输出电流进行。

    Charge pumping circuit
    5.
    发明申请
    Charge pumping circuit 有权
    充电泵电路

    公开(公告)号：US20070183175A1

    公开(公告)日：2007-08-09

    申请号：US11637687

    申请日：2006-12-13

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    IPC分类号： H02M7/00

    CPC分类号： H02M3/07 ,  H03L7/0895 ,  H03L7/0896

    摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

    摘要翻译： 电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。 推挽操作中的另一个用电流镜电路的输出电流进行。

    Charge pump circuit
    6.
    发明授权
    Charge pump circuit 有权
    电荷泵电路

    公开(公告)号：US08040168B2

    公开(公告)日：2011-10-18

    申请号：US11188855

    申请日：2005-07-26

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    IPC分类号： H03L7/06 ,  G05F3/02

    CPC分类号： H02M3/07

    摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

    摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

    Charge pump circuit
    7.
    发明申请
    Charge pump circuit 有权
    电荷泵电路

    公开(公告)号：US20060097772A1

    公开(公告)日：2006-05-11

    申请号：US11188855

    申请日：2005-07-26

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

    摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

    Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit
    8.
    发明申请
    Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
    低通滤波器，用于pll，锁相环和半导体集成电路

    公开(公告)号：US20050077955A1

    公开(公告)日：2005-04-14

    申请号：US10500875

    申请日：2003-05-22

    申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

    发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

    IPC分类号： H03H11/12 ,  H03H11/04 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03B1/00

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

    摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

    摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

    Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit
    9.
    发明授权
    Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
    用于PLL，锁相环和半导体集成电路的低通滤波器

    公开(公告)号：US07030688B2

    公开(公告)日：2006-04-18

    申请号：US10500875

    申请日：2003-05-22

    申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

    发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

    IPC分类号： H03K5/00

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

    摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

    摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。