公开(公告)号：US08266367B2

公开(公告)日：2012-09-11

申请号：US12475457

申请日：2009-05-29

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Myeongjin Shin

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Myeongjin Shin

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0688 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C11/5678 ,  G11C13/0004 ,  G11C29/765

摘要： Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.

摘要翻译： 截断将所有闪存通道的可用条带数据容量减小到最小闪存通道的容量。 固态磁盘（SSD）具有智能存储交换机，通过截断来保护从条带数据容量中移除的闪存存储。 超出条带数据容量的额外存储被访问为不带条纹的分散数据。 随着更多的坏块出现，条带数据容量的大小随着时间的推移而减少。 一级条形图存储所有闪存通道的条纹和分散容量，并映射散射和条纹数据。 每个闪存通道都具有一个非易失性存储器件（NVMD），该器件具有将逻辑块地址（LBA）转换为访问NVMD中闪存的物理块地址（PBA）的低级别控制器。 磨损平整和坏块重映射由每个NVMD进行。 源和阴影闪存块由NVMD回收。 两级智能存储交换机支持三级控制器。

公开(公告)号：US08060670B2

公开(公告)日：2011-11-15

申请号：US12717918

申请日：2010-03-04

申请人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

发明人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

IPC分类号： G06F12/02 ,  G06F13/36 ,  G06F3/00

CPC分类号： G06F13/1684 ,  G11C16/102 ,  G11C2216/30

摘要： Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.

摘要翻译： 公开了在基于UAS的闪存设备中存储和访问数据的方法和系统。 基于UAS的闪存设备包括控制器和它控制的多个非易失性存储器（例如闪存）。 控制器被配置为经由物理层（例如，基于USB 3.0的插头和线路）连接到UAS主机，并且用于经由两组逻辑管道进行数据传输操作。 控制器还包括随机存取存储器（RAM）缓冲器，其配置用于通过逻辑管道集合实现并行和双工数据传输操作。 此外，控制器中还包括配置用于连接多个非易失性存储设备的智能存储交换机。 最后，通过设备的用户认证数据加密/解密来提供用于数据安全的安全模块/引擎/单元。 此外，闪速存储器件包括被配置用于光学连接到也配置有光收发器的主机的光收发器。

公开(公告)号：US08037234B2

公开(公告)日：2011-10-11

申请号：US12252155

申请日：2008-10-15

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F3/0607 ,  G06F3/0632 ,  G06F12/0607 ,  G06F2212/1036 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C13/0004

摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

摘要翻译： 闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。 闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。 智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。 剩余部分指向SDRAM中主机数据的位置。 命令队列存储主机命令的Q，R。

公开(公告)号：US20110066837A1

公开(公告)日：2011-03-17

申请号：US12947211

申请日：2010-11-16

申请人： Charles C. Lee ,  Abraham C. Ma ,  Frank Yu ,  Shimon Chen

发明人： Charles C. Lee ,  Abraham C. Ma ,  Frank Yu ,  Shimon Chen

IPC分类号： G06F15/177 ,  G06F12/02 ,  G06F13/28 ,  G06F9/24

CPC分类号： G06F9/4401 ,  G06F13/387 ,  G06F2213/3854

摘要： A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.

摘要翻译： 多媒体卡（MMC）单片闪存器件（SCFD）包含一个MMC闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。 引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。

公开(公告)号：US20110016267A1

公开(公告)日：2011-01-20

申请号：US12887477

申请日：2010-09-21

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F13/28 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14

摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

摘要翻译： 闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。 批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。 状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。 来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。 数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。 使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

公开(公告)号：US20100275037A1

公开(公告)日：2010-10-28

申请号：US12831160

申请日：2010-07-06

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Shimon Chen

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Shimon Chen

IPC分类号： G06F13/36 ,  G06F13/10 ,  G06F1/04 ,  G06F13/28 ,  H04L9/00 ,  G06F1/32

CPC分类号： G06F13/385 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

摘要： A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.

摘要翻译： 低功耗闪存设备使用修改后的通用串行总线（USB）3.0协议来降低功耗。 当应用程序中的USB电缆长度短时，位时钟减慢了功率，并且需要预加重。 通过消除8/10位编码器并将同步和成帧字节编码为9位符号来提高数据效率。 数据字节只有在数据中出现一系列6个数据字节时才能通过位填充进行扩展。 标头和有效载荷数据以每个数据字节近8位的形式传输，而成帧是每个符号9位，远远小于每个字节的标准10位。 使用低功率链路层，物理层和缩小协议层。 读卡器转换器集线器允许USB主机访问低功耗USB设备。 只有一个闪存设备被访问，与标准的USB广播相比，将功耗降低到多个设备。

公开(公告)号：US07809862B2

公开(公告)日：2010-10-05

申请号：US12426189

申请日：2009-04-17

申请人： I-Kang Frank Yu ,  Abraham C. Ma ,  Charles C. Lee

发明人： I-Kang Frank Yu ,  Abraham C. Ma ,  Charles C. Lee

IPC分类号： G06F3/00 ,  G06F13/36

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是可随机寻址的闪存阵列。 来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。 响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US07643334B1

公开(公告)日：2010-01-05

申请号：US11836264

申请日：2007-08-09

申请人： Charles C. Lee ,  Abraham C. Ma ,  Edward W. Lee

发明人： Charles C. Lee ,  Abraham C. Ma ,  Edward W. Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C7/22 ,  G11C13/0069 ,  G11C2213/79

摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time depends on the write data state and is relatively long for set, but short for clear. A PCM chip has a lookup table (LUT) caching write data that is later written to a PCM bank. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the slower PCM. The PCM chip has upstream and downstream serial interfaces to other PCM chips arranged as a token stub. Requests are passed down the token-stub while acknowledgements are passed up the token-stub to the host's memory controller. Shared chip-enable lines are driven by the upstream PCM chip for requests, and by the downstream PCM chip for acknowledgements.

摘要翻译： 相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。 存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。 写入时间取决于写入数据状态，并且对于设置来说相对较长，但是要清除。 PCM芯片具有一个查找表（LUT），用于缓存稍后写入PCM存储区的写入数据。 主机数据被锁存在行FIFO中并被写入LUT中，从而减少对较慢PCM的写延迟。 PCM芯片具有排列成令牌存根的其他PCM芯片的上游和下游串行接口。 请求在令牌存根下传递，而确认将令牌存根传递到主机的内存控制器。 共享芯片使能线由上行PCM芯片驱动，用于请求，由下行PCM芯片用于确认。

公开(公告)号：US20090240865A1

公开(公告)日：2009-09-24

申请号：US12426189

申请日：2009-04-17

申请人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

发明人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

IPC分类号： G06F13/00 ,  G06F13/20

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。 响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20090204872A1

公开(公告)日：2009-08-13

申请号：US12427675

申请日：2009-04-21

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

IPC分类号： G06F12/08 ,  G06F12/02 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0607 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C7/00 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/0483

摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.