公开(公告)号：US5933020A

公开(公告)日：1999-08-03

申请号：US731528

申请日：1996-10-16

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G01R27/02 ,  G01R31/28 ,  H01L23/544 ,  G01R31/22

CPC classification number: H01L22/34 ,  G01R27/02 ,  G01R31/2831 ,  H01L2924/0002

Abstract: A device and method for determining parasitic resistances in a metal oxide silicon field effect transistor (MOSFET). In one embodiment of the present invention, respective total resistances between a plurality of pairs of varyingly spaced apart first contacts of a first test structure are measured. The contact resistance between the plurality of first contacts and a first silicided region and a sheet resistance per unit length of the first silicided region are calculated from the previously measured respective total resistances. Next, respective total resistances between a plurality of pairs of varyingly spaced apart second contacts of a second test structure are measured. The present invention then calculates from the previously measured respective total resistances various resistance components contributing to a total resistance between any pair of the plurality of second contacts. The present invention then subtracts, from the total resistance between any two of the plurality of second contacts, the contact resistance between the plurality of first contacts and the first silicided region and the sheet resistance per unit length of the first silicided region. In so doing, the present invention determines the contact resistance between each of a plurality of second silicided regions and a respective adjacent lightly doped drain region. The present invention also determines a sheet resistance across any one of the respective lightly doped drain regions.

Abstract translation: 一种用于确定金属氧化物硅场效应晶体管（MOSFET）中的寄生电阻的装置和方法。 在本发明的一个实施例中，测量第一测试结构的多对成对间隔开的第一触点之间的总电阻。 从先前测量的相应的总电阻计算出多个第一触点与第一硅化区之间的接触电阻和第一硅化区的每单位长度的薄层电阻。 接下来，测量第二测试结构的多对间隔开的第二接触件之间的总电阻。 然后，本发明根据先前测量的各个总电阻计算有助于任何一对多个第二触点之间的总电阻的各种电阻分量。 然后，本发明从多个第二触点中的任意两个之间的总电阻中减去多个第一触点与第一硅化区之间的接触电阻和第一硅化区的每单位长度的薄层电阻。 这样做，本发明确定了多个第二硅化物区域和各个相邻的轻掺杂漏极区域中的每一个之间的接触电阻。 本发明还确定跨过各个轻掺杂漏极区域中的任何一个的薄层电阻。

公开(公告)号：US5928968A

公开(公告)日：1999-07-27

申请号：US995500

申请日：1997-12-22

Applicant: Subhas Bothra ,  Harlan Lee Sur, Jr.

Inventor： Subhas Bothra ,  Harlan Lee Sur, Jr.

IPC: B81B3/00 ,  G01L9/00 ,  H01L21/00

CPC classification number: B81C1/00047 ,  G01L9/0042 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2207/07

Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7. In this manner, the tungsten plug will come in direct contact with the basic solution that causes the tungsten plug to be removed while the pressure transducer structure is submerged in the basic solution.

Abstract translation: 公开了一种在CMOS集成电路中制造半导体压力传感器结构的方法。 该方法包括图案化位于第一氧化物层之上的第一金属化层以产生不与衬底电接触的第一图案化金属化层。 在覆盖在第一图案化金属化层上的第二氧化物层中形成钨插塞，使得钨插塞与第一图案化金属化层电接触。 将第二金属化层图案化成覆盖在第一图案化金属化层和钨插塞上以产生第二图案化金属化层。 第二金属化层的图案化被配置为防止第二图案化金属化层完全覆盖钨插塞。 该方法还包括将压力传感器结构浸入具有大于约7的pH水平的碱性溶液中。以这种方式，钨塞将与基本溶液直接接触，导致钨丝塞被去除，而 压力传感器结构浸没在基本解决方案中。

公开(公告)号：US5880519A

公开(公告)日：1999-03-09

申请号：US856949

申请日：1997-05-15

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/58 ,  H01L23/52 ,  H01L23/69

CPC classification number: H01L23/564 ,  H01L23/291 ,  H01L2924/0002

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer. Further, the method includes depositing a second silicon nitride layer over the oxide material that is applied by the deposition component and the edge of the first silicon nitride layer sputtered by the sputtering component to establish a moisture and mobile ion repelling barrier between the second and first silicon nitride layers.

公开(公告)号：US5834356A

公开(公告)日：1998-11-10

申请号：US883814

申请日：1997-06-27

Applicant: Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

Inventor： Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/20

CPC classification number: H01L28/24 ,  H01L21/28518 ,  H01L28/20

Abstract: Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed. Further, the method includes etching the substrate in order to remove the exposed metallization silicided layer overlying the at least one active device to produce a substantially increased level of sheet resistance over the at least one active device not having the metallization silicided layer.

Abstract translation: 本发明公开了一种在水银工艺中制作高电阻结构的方法。 该方法包括提供包括至少一个具有扩散区的有源器件和多晶硅栅极结构的衬底。 在包括至少一个有源器件的衬底上沉积金属化层。 退火衬底以使至少部分金属化层在包括至少一个有源器件的衬底上形成金属化硅化物层。 优选地，位于扩散区域和多晶硅栅极上方的金属化硅化物层产生显着降低的薄层电阻水平。 该方法还包括在金属化硅化物层上形成掩模，并且掩模被配置为留下覆盖至少一个暴露的有源器件的金属化硅化物层的一部分。 此外，该方法包括蚀刻衬底以去除覆盖至少一个有源器件的暴露的金属化硅化物层，以在不具有金属化硅化物层的至少一个有源器件上产生基本上增加的片电阻水平。

公开(公告)号：US5798559A

公开(公告)日：1998-08-25

申请号：US922953

申请日：1997-09-03

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L23/4821 ,  H01L23/5221 ,  H01L2924/0002 ,  Y10S438/926

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and nonsacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer. Additional similar interconnect structures can be stacked over a base interconnect structure.

Abstract translation: 制造具有空气作为金属化层之间的有效电介质的集成电路互连结构的方法包括以下步骤：a）在衬底上提供牺牲材料的空气电介质形成层; b）在空气电介质形成层中形成柱孔; c）用非牺牲材料填充柱孔; d）在牺牲空气电介质形成层和非空隙材料柱之上构建金属化层; 以及e）向互连结构施加各向同性蚀刻剂以除去牺牲材料，留下用于金属化层的机械支撑的非牺牲材料柱。 具有空气电介质的互连结构包括底部金属化层，顶部金属化层和分离底部和顶部金属化层并机械地支撑顶部金属化层的多个柱。 附加的类似互连结构可以堆叠在基底互连结构上。

公开(公告)号：US5618757A

公开(公告)日：1997-04-08

申请号：US593898

申请日：1996-01-30

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L21/3105 ,  H01L21/302 ,  H01L21/304 ,  H01L21/463

CPC classification number: H01L21/31053 ,  Y10S438/926 ,  Y10S438/941

Abstract: Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised areas are formed from a metallic material that is deposited in one single step with an oxide layer deposited over both the active conductive traces and the dummy raised areas prior to the application of spin-on glass and the spin-on glass etchback process. In other applications, the dummy raised areas are formed from an oxide material.

Abstract translation: 旋转玻璃回蚀是通常用于在制造期间平面化半导体晶片的表面的技术。 旋涂玻璃的蚀刻速率很大程度上受到旋涂玻璃回蚀工艺中暴露的氧化物的影响。 在旋涂玻璃回蚀期间暴露的氧化物的量取决于地形的底层图案密度。 公开了一种标准化不同层半导体晶片的形貌图案密度的方法，以改善用于在处理期间平坦化晶片表面的旋涂玻璃回蚀工艺。 为了实现晶片表面的标准图案密度，虚拟凸起区域被添加到迹线层上的有源导电迹线之间的间隙中。 在一些实施方案中，标准化图案密度在约40％至80％的范围内。 在一些应用中，有源导电迹线和虚拟凸起区域均由金属材料形成，该金属材料在施加旋转之前沉积在两个有源导电迹线和虚拟凸起区域上的一个单一步骤中沉积， 在玻璃上和旋涂玻璃回蚀工艺。 在其他应用中，虚拟凸起区域由氧化物材料形成。

公开(公告)号：US5597668A

公开(公告)日：1997-01-28

申请号：US504157

申请日：1995-07-19

Applicant: Edward D. Nowak ,  Subhas Bothra ,  David Eatock ,  Wesley Erck

Inventor： Edward D. Nowak ,  Subhas Bothra ,  David Eatock ,  Wesley Erck

IPC: G03F1/00 ,  G03F7/09 ,  G03F9/00

CPC classification number: G03F1/70 ,  G03F7/094

Abstract: The planarity of the dielectric layer over a processing layer is increased by adjustments made to a mask generated for patterning the processing layer. Active circuitry lines are generated for the mask. Also, a fill pattern is generated for the mask. The fill pattern is placed in areas of the mask not filled by the active circuitry lines. The active circuitry lines are combined with the fill pattern to produce a final pattern for the mask. In one embodiment, the fill pattern is generated by first over-sizing the active circuitry lines to form a first pattern. The first pattern is inverted to produce a negative of the first pattern. The negative of the first pattern serves as a marker layer. In addition, a dummy fill pattern is generated. An intersection of the marker layer and the dummy fill pattern is performed to produce an unsized fill pattern. Areas which have widths smaller than a predetermined minimum width and areas which have heights smaller than a predetermined minimum height are eliminated from the unsized fill pattern to produce the final fill pattern. The union of the original active circuitry lines and the final fill pattern forms a composite pattern for the photomask.

Abstract translation: 介电层在处理层上的平面度通过对为图案化处理层而产生的掩模进行调整而增加。 为掩模生成有源电路线。 此外，为掩模生成填充图案。 填充图案被放置在未被有源电路线填充的掩模的区域中。 有源电路线与填充图案组合以产生掩模的最终图案。 在一个实施例中，通过首先超量化有源电路线以形成第一图案来生成填充图案。 第一图案被反转以产生第一图案的否定。 第一图案的负值用作标记​​层。 另外，生成虚拟填充图案。 执行标记层和虚拟填充图案的交叉点以产生未填充图案。 具有小于预定最小宽度的宽度的区域和具有小于预定最小高度的高度的区域从未填充图案中消除以产生最终填充图案。 原始有源电路线和最终填充图案的并集形成光掩模的复合图案。