公开(公告)号：US6057224A

公开(公告)日：2000-05-02

申请号：US899531

申请日：1997-07-24

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L21/44 ,  H01L21/461

CPC classification number: H01L21/7682 ,  H01L23/4821 ,  H01L23/5221 ,  H01L2924/0002 ,  Y10S438/926

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer. Additional similar interconnect structures can be stacked over a base interconnect structure.

Abstract translation: 制造具有空气作为金属化层之间的有效电介质的集成电路互连结构的方法包括以下步骤：a）在衬底上提供牺牲材料的空气电介质形成层; b）在空气电介质形成层中形成柱孔; c）用非牺牲材料填充柱孔; d）在牺牲空气电介质形成层和非牺牲材料柱之上构建金属化层; 以及e）向互连结构施加各向同性蚀刻剂以除去牺牲材料，留下用于金属化层的机械支撑的非牺牲材料柱。 具有空气电介质的互连结构包括底部金属化层，顶部金属化层和分离底部和顶部金属化层并机械地支撑顶部金属化层的多个柱。 附加的类似互连结构可以堆叠在基底互连结构上。

公开(公告)号：US6046102A

公开(公告)日：2000-04-04

申请号：US196481

申请日：1998-11-19

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/4763 ,  H01L21/31

CPC classification number: H01L23/564 ,  H01L23/291 ,  H01L2924/0002

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer. Further, the method includes depositing a second silicon nitride layer over the oxide material that is applied by the deposition component and the edge of the first silicon nitride layer sputtered by the sputtering component to establish a moisture and mobile ion repelling barrier between the second and first silicon nitride layers.

Abstract translation: 公开了一种制备钝化涂层半导体结构的方法。 该方法包括提供具有在衬底上图案化的金属化线的衬底。 金属化线限定具有第一厚度的至少一个互连特征，以及在衬底和金属化线上沉积具有第二厚度的第一氮化硅阻挡层。 所述方法还包括在覆盖在衬底和金属化线上的第一氮化硅阻挡层上施加氧化物材料。 氧化物应用包括沉积部件和溅射部件，并且溅射部件被配置为去除第一氮化硅层的边缘的至少一部分。 边缘由第一氮化硅层下面的金属化线限定。 此外，该方法包括在由沉积部件施加的氧化物材料上沉积第二氮化硅层和由溅射部件溅射的第一氮化硅层的边缘，以在第二和第一之间建立湿气和可移动的离子排斥势垒 氮化硅层。

公开(公告)号：US5965218A

公开(公告)日：1999-10-12

申请号：US819283

申请日：1997-03-18

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: G01Q70/06 ,  G01Q60/16 ,  G01Q60/38 ,  G01Q70/14 ,  G01Q70/16 ,  B05D5/12 ,  H01J9/04 ,  H05H1/24

CPC classification number: G01Q60/16 ,  B82Y35/00 ,  G01Q60/38 ,  H01J2209/022

Abstract: A method for manufacturing probe tips suitable for use in an atomic force microscope (AFM) or scanning tunneling microscope (STM) begins by depositing a layer of a first material over a substrate and then patterning the layer of the first material to define apertures wherever probe tips are to be formed. Next, a layer of a second material is deposited using an unbiased high density plasma chemical vapor deposition (HDPCVD) process to form sharp probe tips in the apertures in the layer of the first material. The HDPCVD process also forms a sacrificial layer of the second material on top of the portions of the first material not removed by the patterning step. The sacrificial layer at least partially overhangs the apertures in the first material, forming a shadow mask during the deposition process which gives rise to a sharp probe profile. After the formation of the probe tips, the remaining portion of the layer of first material is removed using a wet chemical etchant that selectively etches the first material at a much higher rate than the second material. The removing step also removes the sacrificial layer of the second material because the sacrificial layer is lifted off the substrate when the underlying layer of first material is etched away. In one preferred embodiment, the first material is silicon nitride and the second material is silicon dioxide.

Abstract translation: 用于制造适于在原子力显微镜（AFM）或扫描隧道显微镜（STM）中使用的探针尖端的方法开始于在衬底上沉积第一材料层，然后对第一材料的层进行图案以在探针 要形成技巧。 接下来，使用无偏高密度等离子体化学气相沉积（HDPCVD）工艺沉积第二材料层，以在第一材料层中的孔中形成尖锐的探针尖端。 HDPCVD工艺还在未被图案化步骤去除的第一材料的部分的顶部上形成第二材料的牺牲层。 牺牲层至少部分地悬挂在第一材料中的孔中，在沉积过程期间形成荫罩，其产生尖锐的探针轮廓。 在形成探针尖端之后，使用湿化学蚀刻剂去除第一材料层的剩余部分，其以比第二材料高得多的速率选择性地蚀刻第一材料。 当第一材料的下层被蚀刻掉时，去除步骤也会去除第二材料的牺牲层，因为牺牲层被从衬底上提起。 在一个优选实施例中，第一材料是氮化硅，第二材料是二氧化硅。

公开(公告)号：US5880519A

公开(公告)日：1999-03-09

申请号：US856949

申请日：1997-05-15

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/58 ,  H01L23/52 ,  H01L23/69

CPC classification number: H01L23/564 ,  H01L23/291 ,  H01L2924/0002

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer. Further, the method includes depositing a second silicon nitride layer over the oxide material that is applied by the deposition component and the edge of the first silicon nitride layer sputtered by the sputtering component to establish a moisture and mobile ion repelling barrier between the second and first silicon nitride layers.

公开(公告)号：US5798559A

公开(公告)日：1998-08-25

申请号：US922953

申请日：1997-09-03

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L23/4821 ,  H01L23/5221 ,  H01L2924/0002 ,  Y10S438/926

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and nonsacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer. Additional similar interconnect structures can be stacked over a base interconnect structure.

Abstract translation: 制造具有空气作为金属化层之间的有效电介质的集成电路互连结构的方法包括以下步骤：a）在衬底上提供牺牲材料的空气电介质形成层; b）在空气电介质形成层中形成柱孔; c）用非牺牲材料填充柱孔; d）在牺牲空气电介质形成层和非空隙材料柱之上构建金属化层; 以及e）向互连结构施加各向同性蚀刻剂以除去牺牲材料，留下用于金属化层的机械支撑的非牺牲材料柱。 具有空气电介质的互连结构包括底部金属化层，顶部金属化层和分离底部和顶部金属化层并机械地支撑顶部金属化层的多个柱。 附加的类似互连结构可以堆叠在基底互连结构上。

公开(公告)号：US20110163831A1

公开(公告)日：2011-07-07

申请号：US13047699

申请日：2011-03-14

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US07614024B2

公开(公告)日：2009-11-03

申请号：US11244514

申请日：2005-10-06

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Abstract translation: 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US20060273874A1

公开(公告)日：2006-12-07

申请号：US11504073

申请日：2006-08-15

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US07095307B1

公开(公告)日：2006-08-22

申请号：US10623084

申请日：2003-07-17

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US06492716B1

公开(公告)日：2002-12-10

申请号：US09846335

申请日：2001-04-30

Applicant: Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

Inventor： Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

IPC: H01L2302

CPC classification number: H01L23/564 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.

Abstract translation: 本发明的实施例提供了一种密封环，其包括将密封环分隔成密封环部分的多个切口，所述密封环部分邻近集成电路管芯中的不同电路设置。 切割可以通过密封环减少不同电路之间的噪声耦合。 为了进一步将敏感的RF /模拟电路与数字电路产生的噪声隔离开，密封环可能是与基板隔离的电气（用于直流噪声）。 这通过例如在密封环和衬底之间插入多晶硅层和栅极氧化物来实现。 此外，n阱/ p阱电容器可以与栅极氧化物串联形成，例如通过在p型衬底中注入多晶硅层下面的n阱。 以这种方式，密封环在电路之间提供显着降低的噪声耦合，但仍然保持围绕芯片周边的有效壁，以保护电路免受潮湿和离子污染的渗透。