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公开(公告)号：US11823769B2
公开(公告)日：2023-11-21
申请号：US17460216
申请日：2021-08-28
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
CPC分类号： G11C7/12 , G11C5/025 , G11C5/14 , H01L27/0688
摘要： Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.
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公开(公告)号：US20230371247A1
公开(公告)日：2023-11-16
申请号：US18357776
申请日：2023-07-24
发明人： Meng-Sheng Chang , Chia-En Huang
IPC分类号： H10B20/20 , H01L23/525
CPC分类号： H10B20/20 , H01L23/5256
摘要： A memory device is disclosed. The memory device includes a transistor. The memory device includes a resistor electrically coupled to the transistor, the transistor and the resistor forming an electrical fuse (eFuse) memory cell. The memory device includes a plurality of interconnect structures formed over a source/drain structure of the transistor. The memory device includes a plurality of via structures formed over the source/drain structure of the transistor. The resistor is disposed between the source/drain structure of the transistor and a topmost one of the plurality of interconnect structures. The resistor is formed of titanium nitride (TiN).
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公开(公告)号：US11756640B2
公开(公告)日：2023-09-12
申请号：US17396398
申请日：2021-08-06
发明人： Meng-Sheng Chang , Chia-En Huang , Yih Wang
CPC分类号： G11C17/165 , H10B20/20
摘要： A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.
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公开(公告)号：US20230066618A1
公开(公告)日：2023-03-02
申请号：US17460938
申请日：2021-08-30
发明人： Perng-Fei Yuh , Meng-Sheng Chang , Tung-Cheng Chang , Yih Wang
摘要： One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.
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公开(公告)号：US20230066081A1
公开(公告)日：2023-03-02
申请号：US17460215
申请日：2021-08-28
发明人： Meng-Sheng Chang , Chia-En HUANG , Yi-Ching LIU , Yih Wang
IPC分类号： G11C5/06
摘要： Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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公开(公告)号：US20230037696A1
公开(公告)日：2023-02-09
申请号：US17587242
申请日：2022-01-28
发明人： Ku-Feng Lin , Perng-Fei Yuh , Meng-Sheng Chang
IPC分类号： G11C17/16
摘要： In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.
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公开(公告)号：US20220383934A1
公开(公告)日：2022-12-01
申请号：US17331340
申请日：2021-05-26
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4096
摘要： In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.
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公开(公告)号：US20220359547A1
公开(公告)日：2022-11-10
申请号：US17874746
申请日：2022-07-27
发明人： Meng-Sheng Chang , Chia-En Huang , Yih Wang
IPC分类号： H01L27/112 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/66 , H01L23/525
摘要： A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.
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公开(公告)号：US20220336031A1
公开(公告)日：2022-10-20
申请号：US17557268
申请日：2021-12-21
摘要： Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.
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公开(公告)号：US11335424B2
公开(公告)日：2022-05-17
申请号：US17233771
申请日：2021-04-19
发明人： Meng-Sheng Chang , Yao-Jen Yang , Min-Shin Wu
IPC分类号： G11C17/16 , G11C11/408 , G11C11/56 , G11C11/4074 , G11C11/4094
摘要： A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.
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