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    Fusible structures
    2.
    发明授权
    Fusible structures 有权

    公开(公告)号：US12237264B2

    公开(公告)日：2025-02-25

    申请号：US18322481

    申请日：2023-05-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Shao-Ting Wu ,  Meng-Sheng Chang ,  Shao-Yu Chou ,  Chung-I Huang

    IPC: H01L23/525 ,  H10B20/25 ,  H01L21/3213

    Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.

    Memory device with improved anti-fuse read current
    4.
    发明授权
    Memory device with improved anti-fuse read current 有权

    公开(公告)号：US12193223B2

    公开(公告)日：2025-01-07

    申请号：US18447638

    申请日：2023-08-10

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yao-Jen Yang ,  Yih Wang

    IPC: H01L23/528 ,  G06F30/392 ,  H10B20/20

    Abstract: A memory device includes a first programming gate-strip for a first anti-fuse structure and a second programming gate-strip for a second anti-fuse structure. In the memory device, a terminal conductor overlies a terminal region between the channel regions of a first transistor and a second transistor. The memory device also includes a group of first programming conducting and a group of second programming conducting lines. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors.

    Memory device with a bias circuit
    5.
    发明授权
    Memory device with a bias circuit 有权

    公开(公告)号：US12190927B2

    公开(公告)日：2025-01-07

    申请号：US17407875

    申请日：2021-08-20

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Gu-Huan Li

    IPC: G11C11/16

    Abstract: A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.

    SEMICONDUCTOR MEMORY DEVICES WITH DIELECTRIC FIN STRUCTURES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES WITH DIELECTRIC FIN STRUCTURES 有权

    公开(公告)号：US20240389310A1

    公开(公告)日：2024-11-21

    申请号：US18784553

    申请日：2024-07-25

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Chun Chung Su ,  Chih-Ching Wang

    IPC: H10B20/20 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A method of fabricating a memory device includes forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures; separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure; forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure; and forming a first interconnect structure coupled to one of the first gate structure or second gate structure. The dielectric structure also extends along the first lateral direction. The first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction.

    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING
    8.
    发明公开
    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING 审中-公开

    公开(公告)号：US20240331771A1

    公开(公告)日：2024-10-03

    申请号：US18741201

    申请日：2024-06-12

    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

    Inventor： Meng-Sheng Chang ,  Chia-En HUANG ,  Yi-Ching LIU ,  Yih WANG

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

    Abstract: Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

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