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公开(公告)号：US20240347090A1
公开(公告)日：2024-10-17
申请号：US18635929
申请日：2024-04-15
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Po-Hao Lee , Ku-Feng Lin , Yi-Chun Shih , Yu-Der Chih
CPC classification number: G11C11/1675 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1673 , H10B61/22 , H10N50/10
Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
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公开(公告)号：US20240321325A1
公开(公告)日：2024-09-26
申请号：US18679395
申请日：2024-05-30
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
IPC: G11C7/06
CPC classification number: G11C7/062
Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
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公开(公告)号：US20240215261A1
公开(公告)日：2024-06-27
申请号：US18596625
申请日：2024-03-06
Inventor： Hsiang-Ku Shen , Ku-Feng Lin , Liang-Wei Wang , Dian-Hau Chen
IPC: H10B61/00 , G11C11/16 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/10 , H10N50/80
CPC classification number: H10B61/22 , G11C11/161 , H01L23/5226 , H01L23/5283 , H10N50/01 , H10N50/10 , H10N50/80
Abstract: A semiconductor package includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first semiconductor substrate, a first bonding structure bonded to the second integrated circuit, a ferromagnetic layer surrounding the first bonding structure, and a memory cell between the first semiconductor substrate and the first bonding structure.
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公开(公告)号：US12014796B2
公开(公告)日：2024-06-18
申请号：US17669628
申请日：2022-02-11
Inventor： Meng-Sheng Chang , Ku-Feng Lin
CPC classification number: G11C7/1012 , G11C7/06 , G11C7/1063 , G11C7/109 , G11C7/1096 , G11C8/08
Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.
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公开(公告)号：US11574676B2
公开(公告)日：2023-02-07
申请号：US17185189
申请日：2021-02-25
Inventor： Hiroki Noguchi , Ku-Feng Lin
Abstract: A memory device is disclosed. The memory device includes at least one reference cell and multiple sense amplifiers. The at least one reference cell having a first terminal coupled to a ground. Each of the sense amplifiers has a first terminal and a second terminal. The first terminal is coupled to one of multiple first data lines, and the second terminal is coupled to a second terminal of the at least one reference cell.
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Patent Agency Ranking
公开(公告)号：US11380415B2
公开(公告)日：2022-07-05
申请号：US17130250
申请日：2020-12-22
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
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公开(公告)号：US20220101890A1
公开(公告)日：2022-03-31
申请号：US17035609
申请日：2020-09-28
Inventor： Ku-Feng Lin
IPC: G11C7/06
Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.
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公开(公告)号：US11081155B2
公开(公告)日：2021-08-03
申请号：US16431158
申请日：2019-06-04
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Po-Hao Lee , Ku-Feng Lin , Yi-Chun Shih , Yu-Der Chih
Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
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公开(公告)号：US20210135093A1
公开(公告)日：2021-05-06
申请号：US17032638
申请日：2020-09-25
Inventor： Ku-Feng Lin
Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.
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公开(公告)号：US12190986B2
公开(公告)日：2025-01-07
申请号：US18447904
申请日：2023-08-10
Inventor： Ku-Feng Lin , Jui-Che Tsai , Perng-Fei Yuh , Yih Wang
Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.
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