公开(公告)号：US11355398B2

公开(公告)日：2022-06-07

申请号：US17027282

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

公开(公告)号：US11322409B2

公开(公告)日：2022-05-03

申请号：US16805832

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lo-Heng Chang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Jung-Hung Chang ,  Pei-Hsun Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/762 ,  H01L29/10 ,  H01L29/08

Abstract: Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.

公开(公告)号：US11302796B2

公开(公告)日：2022-04-12

申请号：US16837883

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/092

Abstract: The present disclosure provides a method of semiconductor fabrication. The method includes forming a fin protruding from a substrate, the fin having a first sidewall and a second sidewall opposing the first sidewall; forming a sacrificial dielectric layer on the first and second sidewalls and a top surface of the fin; etching the sacrificial dielectric layer to remove the sacrificial dielectric layer from the second sidewall of the fin; forming a recess in the fin; growing an epitaxial source/drain (S/D) feature from the recess, the epitaxial S/D feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the sacrificial dielectric layer covers the first sidewall of the epitaxial S/D feature; recessing the sacrificial dielectric layer, thereby exposing the first sidewall of the epitaxial S/D feature; and forming an S/D contact on the first sidewall of the epitaxial S/D feature.

公开(公告)号：US11302693B2

公开(公告)日：2022-04-12

申请号：US17007742

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

公开(公告)号：US11302580B2

公开(公告)日：2022-04-12

申请号：US16888380

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/306 ,  H01L29/06 ,  H01L21/321 ,  H01L27/088 ,  H01L29/78

Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.

公开(公告)号：US20220108984A1

公开(公告)日：2022-04-07

申请号：US17554811

申请日：2021-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/49

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

公开(公告)号：US11296082B2

公开(公告)日：2022-04-05

申请号：US16947377

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

公开(公告)号：US11264327B2

公开(公告)日：2022-03-01

申请号：US16939803

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Chih-Chao Chou ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8238

Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.

公开(公告)号：US11264288B2

公开(公告)日：2022-03-01

申请号：US16381232

申请日：2019-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Wei-Hao Wu ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/423

Abstract: A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.

公开(公告)号：US11257903B2

公开(公告)日：2022-02-22

申请号：US16697647

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Guan-Lin Chen ,  Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap.