公开(公告)号：US20090203200A1

公开(公告)日：2009-08-13

申请号：US12027444

申请日：2008-02-07

申请人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

发明人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

IPC分类号： H01L21/027

CPC分类号： H01L21/32139 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823828

摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

摘要翻译： 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

公开(公告)号：US07569489B2

公开(公告)日：2009-08-04

申请号：US11851464

申请日：2007-09-07

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/302

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

摘要翻译： 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

公开(公告)号：US07566949B2

公开(公告)日：2009-07-28

申请号：US11380692

申请日：2006-04-28

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

公开(公告)号：US20080283962A1

公开(公告)日：2008-11-20

申请号：US11748521

申请日：2007-05-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823878

摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

摘要翻译： 从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。 通过沉积保形介电层在基座上形成延伸基座。 扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。 包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。 在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。 与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。 在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

公开(公告)号：US07452758B2

公开(公告)日：2008-11-18

申请号：US11686013

申请日：2007-03-14

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body and the fin. The planar body extends generally around the medial body. The fin is situated to extend substantially from a first side of the substrate to an opposing second side of the substrate. The fin is substantially perpendicularly disposed with respect to the planar body. The first oxide layer is situated on the planar body between the planar body and the fin. The oxide layer extends substantially around the medial body. The polysilicone gate is situated on the oxide layer to extend substantially from a third side to an opposing fourth side of the substrate. The gate is situated to extend across the fin proximal to a medial portion of an upper surface of the fin. There is also a process for making a FinFET device.

摘要翻译： 有一个FinFET器件。 该器件具有硅衬底，氧化物层和多晶硅栅极。 硅衬底限定平面体，中间体和翅片。 平面体，内侧体和翅片整体连接。 内侧主体连接平面体和翅片。 平面体通常围绕内侧身体延伸。 翅片位于基本上从基板的第一侧延伸到基板的相对的第二侧。 翅片相对于平面主体基本垂直设置。 第一氧化物层位于平面体和翅片之间的平面体上。 氧化物层基本上围绕内侧本体延伸。 多晶硅栅极位于氧化物层上，基本上从衬底的第三侧延伸到相对的第四侧。 闸门位于靠近翅片上表面的中间部分延伸穿过翅片。 还有一种制造FinFET器件的过程。

公开(公告)号：US20080237749A1

公开(公告)日：2008-10-02

申请号：US11692402

申请日：2007-03-28

申请人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

发明人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/76

CPC分类号： H01L21/28044 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/78

摘要： A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.

摘要翻译： 为包括具有NFET有源半导体区域的n型场效应晶体管（“NFET”）和具有PFET有源半导体区域的p型场效应晶体管（“PFET”）的晶体管对，提供栅极导体，其中 NFET和PFET有源半导体区域被隔离区隔开。 NFET栅极在NFET有源半导体区域上的第一方向上延伸。 PFET栅极在PFET有源半导体区域上沿第一方向延伸。 扩散势垒夹在NFET栅极和PFET栅极之间。 连续层在NFET栅极和PFET栅极上在第一方向上连续延伸。 连续层接触NFET栅极和PFET栅极的顶表面，并且连续层包括半导体，金属或包括金属的导电化合物中的至少一种。

公开(公告)号：US20080237726A1

公开(公告)日：2008-10-02

申请号：US11692371

申请日：2007-03-28

申请人： Thomas W. Dyer

发明人： Thomas W. Dyer

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843 ,  Y10S438/938

摘要： A stress-concentrating spacer structure is a stack of an upper gate spacer with a low Young's modulus and a lower gate spacer with a high Young's modulus. The stacked spacer structure surrounds the gate electrode. The stress-concentrating spacer structure may contact an inner gate spacer that contacts the gate electrode or may directly contact the gate electrode. The upper gate spacer deforms substantially more than the lower gate spacer. The stress generated by the stress liner is thus transmitted primarily through the lower gate spacer to the gate electrode and subsequently to the channel of the MOSFET. The efficiency of the transmission of the stress from the stress liner to the channel is thus enhanced compared to conventional MOSFETs structure with a vertically uniform composition within a spacer.

摘要翻译： 应力集中的间隔结构是具有低杨氏模量的上栅极间隔物和具有高杨氏模量的下栅极间隔物的堆叠。 层叠的间隔结构围绕栅电极。 应力集中的间隔物结构可以接触与栅电极接触的内部栅极间隔物，或者可以直接接触栅电极。 上栅极间隔件基本上比下栅极间隔件更大地变形。 因此，应力衬垫产生的应力主要通过下栅极隔离物传输到栅电极，随后传输到MOSFET的沟道。 因此与在间隔物内具有垂直均匀组成的常规MOSFET结构相比，应力衬底向通道传递应力的效率得到提高。

公开(公告)号：US20080179678A1

公开(公告)日：2008-07-31

申请号：US11627653

申请日：2007-01-26

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L27/0694 ,  H01L21/84 ,  H01L27/1203

摘要： Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.

摘要翻译： 利用绝缘体上半导体衬底的两侧形成MOSFET结构。 在第一半导体层上形成第一类型器件之后，把手晶片结合到第一中间线介电层的顶部。 然后移除载体衬底的下部以暴露第二半导体层并在其上形成第二类型器件。 可以通过掩埋绝缘体层形成导电孔，以电连接第一类型器件和第二类型器件。 掩模掩模的使用最小化，因为埋入绝缘体的每一侧只有一种类型的器件。 结构中存在两级装置，减少或消除不同类型装置之间的边界区域，从而提高装置的包装密度。 可以使用相同的对准标记来将晶片的前侧向上或向后对准。

公开(公告)号：US07393746B2

公开(公告)日：2008-07-01

申请号：US11548870

申请日：2006-10-12

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee ,  JunJung Kim

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee ,  JunJung Kim

IPC分类号： H01L21/33

CPC分类号： H01L21/32 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

摘要翻译： 一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。 然后，该方法在衬底的暴露区域的表面上形成硅化物。 该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。 接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。 随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。 该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。 由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

公开(公告)号：US20080054413A1

公开(公告)日：2008-03-06

申请号：US11468536

申请日：2006-08-30

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L21/76829 ,  H01L21/823807 ,  H01L29/7843

摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.

摘要翻译： 提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。 该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。 还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。