公开(公告)号：US07645658B2

公开(公告)日：2010-01-12

申请号：US11976216

申请日：2007-10-23

申请人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

发明人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

IPC分类号： H01L21/8238

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film. Furthermore, a dehydration process is performed at about 700° C. or lower in an inert gas atmosphere after the reflow process is performed.

摘要翻译： 制造具有MOS结构的碳化硅半导体器件的方法包括制备由碳化硅制成的衬底，并形成沟道区，第一杂质区，第二杂质区，栅绝缘层和栅电极，以形成 半导体元件。 此外，在半导体元件上形成膜以提供层间绝缘层的材料，并且在湿气氛中在约700℃或更高的温度下进行回流工艺，使得层间绝缘层由 这个电影。 此外，在进行回流处理之后，在惰性气体气氛中，在约700℃以下进行脱水处理。

公开(公告)号：US20090283804A1

公开(公告)日：2009-11-19

申请号：US12509239

申请日：2009-07-24

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/148 ,  H01L31/18

CPC分类号： H01L27/14812 ,  H01L27/14837 ,  H01L31/035281 ,  H01L31/03529 ,  Y02E10/50

摘要： It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including: a first conductive type semiconductor layer; a first conductive type pillar-shaped semiconductor layer formed on the first conductive type semiconductor layer; a second conductive type photoelectric conversion region formed on the top of the first conductive type pillar-shaped semiconductor layer, an electric charge amount of the photoelectric conversion region being changed by light; and a high-concentrated impurity region of the first conductive type formed on a surface of the second conductive type photoelectric conversion region, the impurity region being spaced apart from a top end of the first conductive type pillar-shaped semiconductor layer by a predetermined distance, wherein a transfer electrode is formed on the side of the first conductive type pillar-shaped semiconductor layer via a gate insulating film, a second conductive type CCD channel region is formed below the transfer electrode, and a read channel is formed in a region between the second conductive type photoelectric conversion region and the second conductive type CCD channel region.

摘要翻译： 本发明的目的是提供一种CCD固态图像传感器，其中读取通道的面积减小，并且光接收部分（光电二极管）到一个像素的区域的表面积的比率增加。 提供了一种固态图像传感器，包括：第一导电型半导体层; 形成在第一导电型半导体层上的第一导电型柱状半导体层; 第二导电型光电转换区，形成在第一导电型柱状半导体层的顶部，光电转换区域的电荷量由光改变; 以及形成在所述第二导电型光电转换区域的表面上的所述第一导电类型的高浓度杂质区域，所述杂质区域与所述第一导电型柱状半导体层的顶端隔开预定距离， 其中，在所述第一导电型柱状半导体层的侧面经由栅极绝缘膜形成有转印电极，在所述转印电极的下方形成第二导电型CCD沟道区，在所述第二导电型柱状半导体层之间的区域形成读取沟道 第二导电型光电转换区域和第二导电型CCD沟道区域。

公开(公告)号：US20090065832A1

公开(公告)日：2009-03-12

申请号：US12268126

申请日：2008-11-10

申请人： Fujio MASUOKA ,  Hiroki Nakamura

发明人： Fujio MASUOKA ,  Hiroki Nakamura

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/14643 ,  H01L27/14679 ,  H01L27/14683

摘要： It is an object of the present invention to provide an image sensor having a high ratio of a surface area of a light receiving element to a surface area of one pixel. The above-described object is achieved by an inventive solid-state imaging device unit comprising solid-state imaging devices arranged on a substrate according to the present invention. The solid-state imaging device comprises a signal line formed on the substrate, an island shaped semiconductor placed over the signal line, and a pixel selection line connected to an upper portion of the island shaped semiconductor. The island shaped semiconductor comprises a first semiconductor layer disposed in a lower portion of the island shaped semiconductor and connected to the signal line, a second semiconductor layer disposed adjacent to an upper side of the first semiconductor layer, a gate connected to the second semiconductor layer via an insulating film, an electric charge accumulator comprising a third semiconductor layer connected to the second semiconductor layer and carrying a quantity of electric charges which varies in response to a light reception, and a fourth semiconductor layer disposed adjacent to an upper side of the second semiconductor layer and the third semiconductor layer and connected to the pixel selection line. The solid-state imaging devices are arranged on the substrate in a honeycomb configuration.

摘要翻译： 本发明的目的是提供一种具有高比率的光接收元件与一个像素的表面积的比率的图像传感器。 上述目的通过本发明的固态成像装置单元实现，该装置包括布置在根据本发明的基板上的固态成像装置。 固态成像装置包括形成在基板上的信号线，放置在信号线上的岛状半导体以及连接到岛状半导体的上部的像素选择线。 岛状半导体包括设置在岛状半导体的下部并连接到信号线的第一半导体层，邻近第一半导体层的上侧设置的第二半导体层，连接到第二半导体层的栅极 通过绝缘膜，电荷累加器，包括连接到第二半导体层的第三半导体层，并且承载响应于光接收而变化的电荷量;以及第四半导体层，邻近第二半导体层 半导体层和第三半导体层，并连接到像素选择线。 固态成像装置以蜂窝结构布置在基板上。

公开(公告)号：US20090057722A1

公开(公告)日：2009-03-05

申请号：US12284327

申请日：2008-09-19

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L27/10

CPC分类号： H01L27/092 ,  H01L21/823885 ,  H01L27/1203 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters are coupled with each other, each of the n inverters has: a pMOS SGT; an nMOS SGT, an input terminal arranged so as to connect a gate of the pMOS SGT with a gate of the nMOS SGT; an output terminal arranged to connect a drain diffusion layer of the pMOS SGT with a drain diffusion layer of the nMOS SGT in an island-shaped semiconductor lower layer; a pMOS SGT power supply wiring line arranged on a source diffusion layer of the pMOS SGT; and an nMOS SGT power supply wiring line arranged on a source diffusion layer of the NMOS SGT, and an n−1th output terminal is connected with an nth input terminal.

摘要翻译： 提供了由至少两级提供的使用SGT的高度集成的高速CMOS反相器耦合电路形成的半导体器件。 根据本发明的半导体器件由CMOS反相器耦合电路形成，其中n（n是两个或更多个）CMOS反相器彼此耦合，每个n个反相器具有：pMOS SGT; nMOS SGT，被配置为将pMOS SGT的栅极与nMOS SGT的栅极连接的输入端子; 输出端子，布置成在岛状半导体下层中连接pMOS SGT的漏极扩散层和nMOS SGT的漏极扩散层; 配置在pMOS SGT的源极扩散层上的pMOS SGT电源布线; 以及配置在NMOS SGT的源极扩散层上的nMOS SGT电源配线，第n输出端与第n输入端子连接。

公开(公告)号：US20080252617A1

公开(公告)日：2008-10-16

申请号：US11868126

申请日：2007-10-05

申请人： Hiroki Nakamura ,  Takashi Nakamura ,  Hirotaka Hayashi ,  Norio Tada ,  Takayuki Imai

发明人： Hiroki Nakamura ,  Takashi Nakamura ,  Hirotaka Hayashi ,  Norio Tada ,  Takayuki Imai

IPC分类号： G06F3/042 ,  G09G3/36

CPC分类号： G06F3/0412 ,  G06F3/042

摘要： In making a contact determination between an object and a display screen, a display apparatus of the present invention is capable of adjusting a region on which to make a contact determination in response to the displayed image in a liquid crystal panel, so that the influence by the displayed image can be suppressed. Moreover, for simplifying the contact determination process, the display apparatus sets solid a region in the picked-up image that is not a target of the contact determination, with a predetermined gradation value.

摘要翻译： 在物体和显示屏幕之间进行接触确定时，本发明的显示装置能够根据液晶面板中显示的图像来调整在其上进行接触确定的区域，从而影响到 可以抑制显示的图像。 此外，为了简化接触确定处理，显示装置以预定的灰度值将不是接触确定的目标的拍摄图像中的区域固定。

公开(公告)号：US20080102585A1

公开(公告)日：2008-05-01

申请号：US11976216

申请日：2007-10-23

申请人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

发明人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

IPC分类号： H01L21/336

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film. Furthermore, a dehydration process is performed at about 700° C. or lower in an inert gas atmosphere after the reflow process is performed.

摘要翻译： 制造具有MOS结构的碳化硅半导体器件的方法包括制备由碳化硅制成的衬底，并形成沟道区，第一杂质区，第二杂质区，栅绝缘层和栅电极，以形成 半导体元件。 此外，在半导体元件上形成膜以提供层间绝缘层的材料，并且在湿气氛中在约700℃或更高的温度下进行回流工艺，使得层间绝缘层由 这个电影。 此外，在进行回流处理之后，在惰性气体气氛中，在约700℃以下进行脱水处理。

公开(公告)号：US20080090383A1

公开(公告)日：2008-04-17

申请号：US11730600

申请日：2007-04-03

申请人： Hiroki Nakamura ,  Yoshihiro Miyoshi ,  Eiichi Okuno

发明人： Hiroki Nakamura ,  Yoshihiro Miyoshi ,  Eiichi Okuno

IPC分类号： H01L21/265 ,  H01L21/304

CPC分类号： H01L21/046 ,  H01L21/324 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828 ,  Y10S438/931

摘要： A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity ion in the SiC layer; forming a carbon layer on the SiC layer; heating the SiC layer for activating the implanted impurity in the SiC layer covered with the carbon layer; and removing the carbon layer from the SiC layer. The forming the carbon layer includes: coating a resist on the SiC layer; and heating the resist for evaporating organic matter in the resist so that the resist is carbonized. The forming the oxide film is performed after the removing the carbon layer.

摘要翻译： 一种制造SiC半导体器件的方法包括：在SiC层中形成杂质层; 在SiC层上形成氧化膜。 形成杂质层包括：在SiC层中注入杂质离子; 在所述SiC层上形成碳层; 加热SiC层以激活被碳层覆盖的SiC层中的注入杂质; 并从SiC层除去碳层。 形成碳层包括：在SiC层上涂覆抗蚀剂; 并加热抗蚀剂以蒸发抗蚀剂中的有机物质，使得抗蚀剂被碳化。 在去除碳层之后进行氧化膜的形成。

公开(公告)号：US07355207B2

公开(公告)日：2008-04-08

申请号：US11135661

申请日：2005-05-24

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US20060178007A1

公开(公告)日：2006-08-10

申请号：US11344014

申请日：2006-02-01

申请人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

发明人： Hiroki Nakamura ,  Masaki Kado ,  Shigeru Aomori

IPC分类号： H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L27/124 ,  H01L27/1292 ,  H01L27/1296 ,  H01L29/458

摘要： A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected with at least one of these electrodes is formed by a method comprising forming a pattern of copper seed layer, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating.

摘要翻译： 一种形成铜布线层的方法，其包括在基板上形成铜籽晶层的图案，并通过无电镀在铜籽晶层的图案上形成铜布线图案。 通过包括形成铜籽晶层的图案的方法，形成从由栅电极，源电极，漏电极和与这些电极中的至少一个连接的布线的组中选择的至少一个半导体器件的组件， 并通过无电镀法在铜籽晶层的图案上形成铜布线图案。

公开(公告)号：US20060071217A1

公开(公告)日：2006-04-06

申请号：US11206271

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

IPC分类号： H01L31/0312

CPC分类号： H01L21/823487 ,  H01L29/7722

摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

摘要翻译： 半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域 。 半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到 来自半导体基底的第二表面的栅极上升金属膜。