公开(公告)号：US10199258B2

公开(公告)日：2019-02-05

申请号：US15384940

申请日：2016-12-20

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Hsien-Shih Chu ,  Ming-Feng Kuo ,  Fu-Che Lee ,  Chien-Ting Ho ,  Chiung-Lin Hsu ,  Feng-Yi Chang ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Chien-Cheng Tsai ,  Chin-Hsin Chiu

IPC: H01L21/762 ,  H01L21/308

Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.

公开(公告)号：US20190013201A1

公开(公告)日：2019-01-10

申请号：US15641235

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/033 ,  H01L27/108

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/10855 ,  H01L27/10894

Abstract: A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

公开(公告)号：US10170310B1

公开(公告)日：2019-01-01

申请号：US15900772

申请日：2018-02-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan

IPC: H01L21/033 ,  H01L27/108 ,  H01L21/768

Abstract: A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.

公开(公告)号：US10103019B1

公开(公告)日：2018-10-16

申请号：US15725258

申请日：2017-10-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/20 ,  H01L21/02 ,  G02B1/11 ,  H01L51/00

Abstract: The present invention provides a method of fabricating a semiconductor structure. Firstly, a substrate is provided, a dense region and an isolation region are defined, next, a first dielectric layer is formed on the dense region and the isolation region, and then a plurality of first recesses are formed in the first dielectric layer within the dense region, and a second recess is formed in the first dielectric layer within the isolation region, wherein the width of the second recess is greater than three times of the width of each first recess. Afterwards, a second dielectric layer is then filled in each first recess and the second recess, wherein a top surface of the second dielectric layer within the isolation region is higher than a top surface of the second dielectric layer within the dense region. Next, an etching back process is performed, to remove the second dielectric layer.

公开(公告)号：US20180226410A1

公开(公告)日：2018-08-09

申请号：US15884415

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

公开(公告)号：US20180190659A1

公开(公告)日：2018-07-05

申请号：US15856024

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chien-Ting Ho ,  Shih-Fang Tzou ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/10855 ,  H01L21/02071 ,  H01L21/28247 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894

Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.

公开(公告)号：US20230369215A1

公开(公告)日：2023-11-16

申请号：US18226750

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/76831 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76224 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US11769727B2

公开(公告)日：2023-09-26

申请号：US17467287

申请日：2021-09-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US11676815B2

公开(公告)日：2023-06-13

申请号：US17234818

申请日：2021-04-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0271 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

公开(公告)号：US20210398902A1

公开(公告)日：2021-12-23

申请号：US17467287

申请日：2021-09-06

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/528 ,  H01L21/311 ,  H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.