公开(公告)号：US09824931B2

公开(公告)日：2017-11-21

申请号：US14981929

申请日：2015-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/49

CPC classification number: H01L21/823481 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.

公开(公告)号：US20170092643A1

公开(公告)日：2017-03-30

申请号：US14864908

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.

公开(公告)号：US20160276429A1

公开(公告)日：2016-09-22

申请号：US14684445

申请日：2015-04-13

Applicant: United Microelectronics Corp.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Rai-Min Huang ,  Chen-Ming Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/7851

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench. The spacer layer is disposed on sidewalls of the trench. The dummy gate structure is disposed across the trench and includes a portion thereof disposed in the trench.

Abstract translation: 半导体器件及其形成方法，半导体器件包括鳍状结构，间隔层和虚拟栅极结构。 鳍状结构设置在基板上，其中鳍状结构具有沟槽。 间隔层设置在沟槽的侧壁上。 伪栅极结构跨越沟槽设置并且包括其设置在沟槽中的部分。

公开(公告)号：US20160260613A1

公开(公告)日：2016-09-08

申请号：US15155064

申请日：2016-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Tsung-Hung Chang ,  I-Ming Tseng

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/26513 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/31116 ,  H01L21/32155 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: The present invention provides a semiconductor structure, comprising at least two gate electrodes disposed on a substrate, wherein each gate electrode is mushroom-shaped and respectively has a salicide region on a top of the gate electrode, wherein the width of the salicide region is larger than the width of the gate electrode. A recess is disposed between each gate electrode, wherein the recess has a recess extension disposed under the salicide region. A spacer fills the extension of the recess, wherein the profile of each gate electrode is a tapered surface, and a contact etching stop layer (CESL) covers the gate electrodes.

Abstract translation: 本发明提供一种半导体结构，其包括设置在基板上的至少两个栅电极，其中每个栅电极是蘑菇状的，并且在栅电极的顶部上分别具有自对准硅化物区域，其中自对准区域的宽度较大 比栅电极的宽度大。 在每个栅电极之间设置凹部，其中凹部具有设置在自对准区域下方的凹陷延伸部。 间隔件填充凹部的延伸部，其中每个栅电极的轮廓是锥形表面，并且接触蚀刻停止层（CESL）覆盖栅电极。

公开(公告)号：US20150140819A1

公开(公告)日：2015-05-21

申请号：US14083456

申请日：2013-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  I-Ming Tseng

IPC: H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/31053 ,  H01L21/76224

Abstract: A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided. A first oxide layer is formed to entirely cover the substrate. A prevention layer is formed on the first oxide layer. A first filling layer is formed on the prevention layer and fills the trenches until the first filling layer is higher than the substrate. A first polishing process is performed to polish the first filling layer until exposing the prevention layer. A second polishing process is performed to polish the first filling layer, the prevention layer and the first oxide layer until the substrate is exposed.

Abstract translation: 半导体工艺包括以下步骤。 提供具有不同尺寸的沟槽的衬底。 形成第一氧化物层以完全覆盖衬底。 在第一氧化物层上形成防止层。 第一填充层形成在预防层上并填充沟槽直到第一填充层高于衬底。 执行第一抛光处理以抛光第一填充层直到暴露预防层。 进行第二抛光处理以抛光第一填充层，防止层和第一氧化物层，直到基板被暴露。