公开(公告)号：US08782356B2

公开(公告)日：2014-07-15

申请号：US13315370

申请日：2011-12-09

申请人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

发明人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

IPC分类号： G06F13/20 ,  G06F13/36 ,  G06F13/18

CPC分类号： G06F13/1621

摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。

公开(公告)号：US08386716B2

公开(公告)日：2013-02-26

申请号：US13292651

申请日：2011-11-09

申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

摘要： Techniques and methods are used to control allocations of cache lines to a higher level cache that have been displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby the displaced cache line castouts are not allocated to the higher level cache. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.

摘要翻译： 技术和方法用于控制高速缓存行分配到从较低级别缓存中移位的更高级缓存。 对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存线的分配，由此不移位的高速缓存行突发不被分配给更高级的高速缓存。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。

公开(公告)号：US06985972B2

公开(公告)日：2006-01-10

申请号：US10264163

申请日：2002-10-03

申请人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

发明人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F13/366 ,  G06F12/0831 ,  G06F2212/1028 ,  G06F2213/0038 ,  Y02D10/13 ,  Y02D10/14

摘要： A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.

摘要翻译： 具有能够动态地启用和禁用其窥探能力（即，窥探检测和响应）的窥探者的数据处理系统。 窥探者通过多个互连连接到总线控制器，包括窥探信号，窥探响应信号和窥探检测信号。 当snooperPresent信号被断言时，后续的窥探请求被发送到snooper，并且窥探者被轮询以进行侦听响应。 每个窥探者都能够在不同的时间进行响应（即，每个窥探者使用不同的侦听延迟进行操作）。 总线控制器单独跟踪snooperPresent信号启用时从每个窥探者接收的窥探响应。 只要窥探者希望取消其窥探能力/操作，窥探者将断言snooperPresent信号。 总线控制器将此识别为snooper不可用的指示。 因此，当总线控制器广播后续的窥探请求时，总线控制器不向窥探者发送窥探请求。

公开(公告)号：US5926831A

公开(公告)日：1999-07-20

申请号：US731350

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215

摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.

摘要翻译： 一种动态配置的存储器控​​制器，用于防止对非良好行为内存的推测性内存访问。 可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。 当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。 提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

公开(公告)号：US20130151799A1

公开(公告)日：2013-06-13

申请号：US13315370

申请日：2011-12-09

申请人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

发明人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

IPC分类号： G06F12/00

CPC分类号： G06F13/1621

摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。

公开(公告)号：US20120059995A1

公开(公告)日：2012-03-08

申请号：US13292651

申请日：2011-11-09

申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.

摘要翻译： 技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。 防止所选线路的分配节省与分配相关联的功率。

公开(公告)号：US06504854B1

公开(公告)日：2003-01-07

申请号：US09058724

申请日：1998-04-10

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Thomas Andrew Sartorius

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Thomas Andrew Sartorius

IPC分类号： H04J306

CPC分类号： G06F13/4059

摘要： A communication system is provided for use in processing systems and the like for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates. at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received and the speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur synchronously at the second clock speed.

摘要翻译： 提供了一种用于处理系统等的通信系统，用于在与第二数据总线相关联的第一数据总线和外围设备之间执行数据传输操作，其中第一数据总线以第一时钟速度操作，并且其中第二数据总线 数据总线运行。 以与第一时钟速度不同的第二时钟速度和第一时钟速度的1 / N整数倍。 接收与第二时钟速度相关联的采样信号，并且响应于采样信号动态地调整外围控制器的状态机的操作速度，使得外围控制器的状态机以第二时钟速度工作并导致 在第二数据总线上的操作以第二时钟速度同步地发生。

公开(公告)号：US5925118A

公开(公告)日：1999-07-20

申请号：US729555

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions. In a preferred embodiment of the present invention, the master function and the slave function are further connected by a plurality of transfer qualifier signals which may specify whether the operation is a read or a write operation, the size of the transfer, the direction of the transfer or the type of transfer so as to further facilitate multiple cycle transfers with a single address specified on the single address bus.

摘要翻译： 通信系统和通信方法，其包括通过单个地址总线，写数据总线和读数据总线连接到主功能的从功能，以便允许在主功能和从机之间重叠多周期读和写操作 功能。 优选地，通信系统包括通过单个地址总线，写数据总线和读数据总线连接到主功能的多个从功能。 多个主功能可以通过总线仲裁器连接到从属功能，总线仲裁器通过地址总线，写数据总线和用于每个主功能的读数据总线连接到多个主功能。 总线仲裁器从多个主功能接收通信操作的请求，并且选择性地将通信操作发送到从属功能。 在本发明的优选实施例中，主功能和从功能还通过多个传输限定符信号进一步连接，传输限定符可以指定操作是读还是写操作，传输的大小，传输的方向 传输或传输类型，以便通过在单个地址总线上指定的单个地址来进一步促进多个周期传输。

公开(公告)号：US5848436A

公开(公告)日：1998-12-08

申请号：US612631

申请日：1996-03-06

申请人： Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F9/34 ,  G06F12/00 ,  G06F12/06

CPC分类号： G06F9/34

摘要： A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.

摘要翻译： 当处理器请求当前未存储在高速缓冲存储器中的特定字时，完成一种使数据线以与处理器修改的小端模式或大端操作模式的数据结构一致的顺序取出的方法和装置 。 请求包括特定字的地址，并且提供关于处理器是否以修改的小端模式或大端模式操作的指示。 存储器管理器在接收到请求时，基于地址和操作模式从存储器（存储设备）检索一行数据。 例如，当使用大端模式时，使用目标字第一排序检索数据行，并且当使用修改的小端模式时，使用反向目标字第一排序来检索数据行。

公开(公告)号：US08880860B2

公开(公告)日：2014-11-04

申请号：US13309623

申请日：2011-12-02

申请人： Thomas Andrew Sartorius ,  Subodh Singh

发明人： Thomas Andrew Sartorius ,  Subodh Singh

IPC分类号： G06F15/177

CPC分类号： G06F11/1441

摘要： A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.

摘要翻译： 处理器复位控制电路被配置为自动捕获存储在一个或多个硬件寄存器中的处理器信息的预复位值，作为复位操作状态机的一部分，并且在将处理器信息改变为其架构上所需的后置复位值之前。 这种预复位处理器信息包括例如处理器程序计数器（PC）的一个或多个预复位值和操作状态模式寄存器的一个或多个预复位值，它们都可以被捕获在一个或多个 更多的预复位捕获存储设备，然后可用于评估目的。 这种预复位捕获存储设备响应于重置来存储预复位信息，并保持所存储的预复位信息直到发生另一个复位。