公开(公告)号：US5926831A

公开(公告)日：1999-07-20

申请号：US731350

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215

摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.

摘要翻译： 一种动态配置的存储器控​​制器，用于防止对非良好行为内存的推测性内存访问。 可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。 当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。 提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

公开(公告)号：US5925118A

公开(公告)日：1999-07-20

申请号：US729555

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions. In a preferred embodiment of the present invention, the master function and the slave function are further connected by a plurality of transfer qualifier signals which may specify whether the operation is a read or a write operation, the size of the transfer, the direction of the transfer or the type of transfer so as to further facilitate multiple cycle transfers with a single address specified on the single address bus.

摘要翻译： 通信系统和通信方法，其包括通过单个地址总线，写数据总线和读数据总线连接到主功能的从功能，以便允许在主功能和从机之间重叠多周期读和写操作 功能。 优选地，通信系统包括通过单个地址总线，写数据总线和读数据总线连接到主功能的多个从功能。 多个主功能可以通过总线仲裁器连接到从属功能，总线仲裁器通过地址总线，写数据总线和用于每个主功能的读数据总线连接到多个主功能。 总线仲裁器从多个主功能接收通信操作的请求，并且选择性地将通信操作发送到从属功能。 在本发明的优选实施例中，主功能和从功能还通过多个传输限定符信号进一步连接，传输限定符可以指定操作是读还是写操作，传输的大小，传输的方向 传输或传输类型，以便通过在单个地址总线上指定的单个地址来进一步促进多个周期传输。

公开(公告)号：US6081860A

公开(公告)日：2000-06-27

申请号：US975545

申请日：1997-11-20

申请人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.

摘要翻译： 一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。 主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。 仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。 主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。 控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。 该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

公开(公告)号：US5862353A

公开(公告)日：1999-01-19

申请号：US823736

申请日：1997-03-25

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/362 ,  G06F13/364 ,  G06F13/372 ,  G06F13/36

CPC分类号： G06F13/364

摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by increasing throughput and decreasing latency while accounting for dynamic changes in bus usage. Devices submit a priority level along with a bus request to a bus controller. Upon receiving multiple requests, an arbiter of the bus controller compares the priority levels associated with the different bus requests and grants control of the bus to the device having the highest priority level. During each cycle that a device has control of the bus, a feedback logic circuit of the bus controller determines whether other bus requests are pending, and if so, determines the highest pending request priority level. Signals corresponding to the results of these determinations are fed back to each device. The device having control of the bus uses the combination of the currently pending request priority level and the device's own latency timer to determine whether it should maintain control of the bus or relinquish control of the bus.

摘要翻译： 具有访问公共共享总线的多个设备的计算机系统中的总线性能可以通过增加吞吐量和减少等待时间来改善，同时考虑总线使用的动态变化。 设备将总线请求提交给总线控制器。 在接收到多个请求时，总线控制器的仲裁器比较与不同总线请求相关联的优先级，并将总线的控制授权给具有最高优先级的设备。 在每个周期中，器件具有对总线的控制，总线控制器的反馈逻辑电路确定其他总线请求是否正在等待，如果是，则确定最高待机请求优先级。 与这些测定结果相对应的信号被反馈给每个设备。 具有总线控制的设备使用当前挂起的请求优先级和设备自身的延迟定时器的组合来确定其是否应该保持对总线的控制或放弃对总线的控制。

公开(公告)号：US06504854B1

公开(公告)日：2003-01-07

申请号：US09058724

申请日：1998-04-10

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Thomas Andrew Sartorius

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Thomas Andrew Sartorius

IPC分类号： H04J306

CPC分类号： G06F13/4059

摘要： A communication system is provided for use in processing systems and the like for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates. at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received and the speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur synchronously at the second clock speed.

摘要翻译： 提供了一种用于处理系统等的通信系统，用于在与第二数据总线相关联的第一数据总线和外围设备之间执行数据传输操作，其中第一数据总线以第一时钟速度操作，并且其中第二数据总线 数据总线运行。 以与第一时钟速度不同的第二时钟速度和第一时钟速度的1 / N整数倍。 接收与第二时钟速度相关联的采样信号，并且响应于采样信号动态地调整外围控制器的状态机的操作速度，使得外围控制器的状态机以第二时钟速度工作并导致 在第二数据总线上的操作以第二时钟速度同步地发生。

公开(公告)号：US5848436A

公开(公告)日：1998-12-08

申请号：US612631

申请日：1996-03-06

申请人： Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F9/34 ,  G06F12/00 ,  G06F12/06

CPC分类号： G06F9/34

摘要： A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.

摘要翻译： 当处理器请求当前未存储在高速缓冲存储器中的特定字时，完成一种使数据线以与处理器修改的小端模式或大端操作模式的数据结构一致的顺序取出的方法和装置 。 请求包括特定字的地址，并且提供关于处理器是否以修改的小端模式或大端模式操作的指示。 存储器管理器在接收到请求时，基于地址和操作模式从存储器（存储设备）检索一行数据。 例如，当使用大端模式时，使用目标字第一排序检索数据行，并且当使用修改的小端模式时，使用反向目标字第一排序来检索数据行。

公开(公告)号：US09092358B2

公开(公告)日：2015-07-28

申请号：US13371506

申请日：2012-02-13

申请人： Bohuslav Rychlik ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  Raymond P. Palma

发明人： Bohuslav Rychlik ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  Raymond P. Palma

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/654

摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

摘要翻译： 用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。 可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。 预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数或基于访问模式动态地改变。 预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

公开(公告)号：US09026744B2

公开(公告)日：2015-05-05

申请号：US11253307

申请日：2005-10-19

申请人： Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Jaya Prakash Subramaniam Ganasan ,  James Norris Dieffenderfer ,  James Edward Sullivan

发明人： Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Jaya Prakash Subramaniam Ganasan ,  James Norris Dieffenderfer ,  James Edward Sullivan

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1621

摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.

摘要翻译： 本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。 处理系统包括多个存储器件和多个处理器。 每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。 处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

公开(公告)号：US08938602B2

公开(公告)日：2015-01-20

申请号：US13565434

申请日：2012-08-02

申请人： Colin Christopher Sharp ,  Thomas Andrew Sartorius

发明人： Colin Christopher Sharp ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/656 ,  Y02D10/13

摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.

摘要翻译： 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性 ，以及定义存储块的物理地址的物理地址位。

公开(公告)号：US08924685B2

公开(公告)日：2014-12-30

申请号：US12777324

申请日：2010-05-11

申请人： Thomas Andrew Sartorius

发明人： Thomas Andrew Sartorius

IPC分类号： G06F12/10 ,  G06F9/34 ,  G06F9/35

CPC分类号： G06F9/34 ,  G06F9/35 ,  G06F12/1027 ,  G06F12/1081 ,  Y02D10/13

摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.

摘要翻译： 描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。 在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。 数据值可以转换为第一个物理地址。 虚拟地址可以转换为第二个物理地址。 第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。