公开(公告)号：US20050237804A1

公开(公告)日：2005-10-27

申请号：US11170880

申请日：2005-06-30

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C7/24 ,  G11C16/00 ,  G11C16/04 ,  G11C16/22 ,  G11C17/00

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

公开(公告)号：US20050138274A1

公开(公告)日：2005-06-23

申请号：US10854397

申请日：2004-05-26

申请人： Luca Santis ,  Tommaso Vali

发明人： Luca Santis ,  Tommaso Vali

IPC分类号： G06F12/14 ,  G11C16/22

CPC分类号： G11C16/22

摘要： A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are coupled to an erase circuit and the remaining N/2 bits are coupled to a programming circuit. After the chip protection register is programmed, the group of N/2 bits coupled to the erase circuit are erased and the remaining N/2 bits are programmed such that an alternating pattern of logical ones and zeros are in the lock bit register. A read and compare circuit generates a lock indication if the alternating pattern is present.

摘要翻译： 芯片保护寄存器锁定电路在锁定位寄存器中使用多个锁定位。 如果寄存器包含N位，则寄存器的N / 2位耦合到擦除电路，剩余的N / 2位耦合到编程电路。 在编程芯片保护寄存器之后，擦除与擦除电路相关的N / 2位的组，并对其余的N / 2位进行编程，使得逻辑1和0的交替模式位于锁定位寄存器中。 如果存在交替模式，则读取和比较电路产生锁定指示。

公开(公告)号：US06898131B2

公开(公告)日：2005-05-24

申请号：US10932858

申请日：2004-09-02

申请人： Giulio G. Marotta ,  Tommaso Vali

发明人： Giulio G. Marotta ,  Tommaso Vali

IPC分类号： G11C7/22 ,  G11C16/32 ,  H03K3/011 ,  H03K3/0231 ,  H03K4/50 ,  G11C16/04

CPC分类号： G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  H03K3/011 ,  H03K3/0231 ,  H03K4/50

摘要： Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

摘要翻译： 具有温度和电压补偿的斜坡比较器脉冲发生器适用于诸如存储器件的集成电路器件。 这种脉冲发生器包括斜坡信号发生器，阈值信号发生器和响应于阈值信号的电位电平和斜坡信号的电位电平之间的差异提供输出信号的比较器。 本文所述的脉冲发生器利用被配置为分压器的自适应阈值信号发生器，并具有具有不同的电阻率有效温度系数的电阻分量。 自适应阈值信号发生器具有串联耦合在高电位节点和低电位节点之间的上电阻分量和下电阻分量。 下电阻分量具有小于上电阻分量的有效电阻率温度系数的电阻率的有效温度系数。

公开(公告)号：US20050041469A1

公开(公告)日：2005-02-24

申请号：US10932489

申请日：2004-09-02

申请人： Giulio Marotta ,  Tommaso Vali

发明人： Giulio Marotta ,  Tommaso Vali

IPC分类号： G11C7/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/06

CPC分类号： G11C7/04 ,  G11C7/14 ,  G11C16/24 ,  G11C16/26

摘要： Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

摘要翻译： 用于感测浮栅存储器单元的编程状态的单端感测装置适用于低电压存储器件。 感测装置具有选择性地耦合到存储单元的输入节点。 感测装置包括用于将预充电电位施加到感测装置的输入节点的预充电路径，用于在感测存储器单元的编程状态之前对位线进行预充电，以及用于将参考电流施加到输入节点的参考电流路径 感测装置。 感测装置还包括感测反相器，其具有耦合到感测装置的输入节点的输入和用于提供指示存储器单元的编程状态的输出信号的输出。 在感测存储器单元的编程状态期间，将参考电流施加到感测装置的输入节点。

公开(公告)号：US06687161B2

公开(公告)日：2004-02-03

申请号：US10036751

申请日：2001-12-21

申请人： Giulio G. Marotta ,  Tommaso Vali

发明人： Giulio G. Marotta ,  Tommaso Vali

IPC分类号： G11C1606

CPC分类号： G11C7/04 ,  G11C7/14 ,  G11C16/24 ,  G11C16/26

摘要： Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

摘要翻译： 用于感测浮栅存储器单元的编程状态的单端感测装置适用于低电压存储器件。 感测装置具有选择性地耦合到存储单元的输入节点。 感测装置包括用于将预充电电位施加到感测装置的输入节点的预充电路径，用于在感测存储器单元的编程状态之前对位线进行预充电，以及用于将参考电流施加到输入节点的参考电流路径 感测装置。 感测装置还包括感测反相器，其具有耦合到感测装置的输入节点的输入和用于提供指示存储器单元的编程状态的输出信号的输出。 在感测存储器单元的编程状态期间，将参考电流施加到感测装置的输入节点。

公开(公告)号：US06643192B2

公开(公告)日：2003-11-04

申请号：US10032277

申请日：2001-12-21

申请人： Giulio G. Marotta ,  Tommaso Vali

发明人： Giulio G. Marotta ,  Tommaso Vali

IPC分类号： G11C1604

CPC分类号： G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  H03K3/011 ,  H03K3/0231 ,  H03K4/50

摘要： Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

摘要翻译： 具有温度和电压补偿的斜坡比较器脉冲发生器适用于诸如存储器件的集成电路器件。 这种脉冲发生器包括斜坡信号发生器，阈值信号发生器和响应于阈值信号的电位电平和斜坡信号的电位电平之间的差异提供输出信号的比较器。 本文所述的脉冲发生器利用被配置为分压器的自适应阈值信号发生器，并具有具有不同的电阻率有效温度系数的电阻分量。 自适应阈值信号发生器具有串联耦合在高电位节点和低电位节点之间的上电阻分量和下电阻分量。 下电阻分量具有小于上电阻分量的有效电阻率温度系数的电阻率的有效温度系数。