公开(公告)号：US07054309B1

公开(公告)日：2006-05-30

申请号：US09991046

申请日：2001-11-21

Applicant: Daryl Hoot ,  William Lo

Inventor： Daryl Hoot ,  William Lo

IPC: H04L2/50 ,  H04J3/16

CPC classification number: H04L69/18 ,  H04L12/2801 ,  H04L69/14 ,  H04L69/324 ,  Y02D50/30

Abstract: A network device includes a media access controller (MAC) and a physical layer having an interface that communicates with the MAC. A first autonegotiation circuit attempts to establish a link using a first transceiver over a first media. A second autonegotiation circuit attempts to establish a link using a second transceiver over a second media. A media selector communicates with the interface and the first and second autonegotiation circuits. The media selector enables data flow from the first media to the MAC using the interface when a link is established first over the first media. The media selector enables data flow from the second media to the MAC using the interface when a link is established first over the second media.

Abstract translation: 网络设备包括媒体接入控制器（MAC）和具有与MAC通信的接口的物理层。 第一自动协商电路尝试使用第一媒体上的第一收发器建立链路。 第二自动协商电路尝试在第二媒体上使用第二收发器建立链路。 媒体选择器与接口和第一和第二自动协商电路进行通信。 当首先在第一媒体上建立链接时，媒体选择器可以使用接口从第一媒体到MAC的数据流。 当首先通过第二媒体建立链路时，媒体选择器使用该接口使得能够从第二媒体到MAC的数据流。

公开(公告)号：US07042893B1

公开(公告)日：2006-05-09

申请号：US10010732

申请日：2001-12-05

Applicant: William Lo ,  Nafea Bishara

Inventor： William Lo ,  Nafea Bishara

IPC: H04L12/28

CPC classification number: G06F13/385 ,  H04J3/0697

Abstract: An SMII interface circuit to communicate data synchronous with a clock signal having a rising edge and a falling edge. The interface circuit includes a transmit circuit that is responsive to the clock signal to generate a first transmit serial stream and a second transmit serial stream. A receive circuit, responsive to the clock signal, to generate a receive serial stream from two receive data streams. The receive serial stream having a operating frequency that is about twice the operating frequency of each of the two receive data streams. Transmit and receive ports corresponding to the transmit and receive circuits each include a single pin to communicate the serial transmit data and the receive serial stream.

Abstract translation: SMII接口电路，用于与具有上升沿和下降沿的时钟信号同步传输数据。 接口电路包括响应于时钟信号以产生第一发送串行流和第二发送串行流的发送电路。 响应于时钟信号的接收电路从两个接收数据流生成接收串行流。 该接收串行流的操作频率大约是两个接收数据流中的每一个的工作频率的两倍。 对应于发送和接收电路的发送和接收端口各自包括用于传送串行发送数据和接收串行流的单个引脚。

公开(公告)号：US06999013B1

公开(公告)日：2006-02-14

申请号：US11190781

申请日：2005-07-27

Applicant: Pierte Roo ,  Francis Campana ,  William Lo

Inventor： Pierte Roo ,  Francis Campana ,  William Lo

IPC: H03M1/88

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: A nonlinearity detection system for an analog to digital converter (ADC) comprises a signal generator that generates a periodic signal that is output to the ADC and that comprises first and second intervals. The periodic signal monotonically increases during the first interval and monotonically decreases during the second interval. A differentiator module communicates with the ADC and that generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.

Abstract translation: 用于模数转换器（ADC）的非线性检测系统包括产生周期性信号的信号发生器，其输出到ADC并且包括第一和第二间隔。 周期性信号在第一个间隔期间单调增加，并在第二个时间间隔内单调减小。 微分器模块与ADC通信，并产生基于ADC的输出和ADC延迟输出的输出信号。 非线性检测模块检测微分器模块的输出信号中的斜率不连续性。

公开(公告)号：US06995551B1

公开(公告)日：2006-02-07

申请号：US11066739

申请日：2005-02-25

Applicant: William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

Inventor： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

IPC: G01R31/11

CPC classification number: G01R31/083 ,  G01R31/088 ,  G01R31/11

Abstract: A physical layer device including a first port, a second port, and a cable that has one end that communicates with the first port and an opposite end that communicates with the second port. A cable tester tests the cable to determine a cable status, which includes an open status, a short status, and a normal status. A pretest module senses activity on the cable and selectively enables testing depending upon the sensed activity. A test module transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer communicates with the cable and that selectively outputs a plurality of signals at a plurality of frequencies on the first port. An insertion loss calculator receives the signals on the second port and that estimates insertion loss.

Abstract translation: 一种包括第一端口，第二端口和具有与第一端口通信的一端的电缆以及与第二端口通信的相对端的物理层设备。 电缆测试仪测试电缆以确定电缆状态，包括打开状态，短状态和正常状态。 预测试模块感测电缆上的活动，并根据感测到的活动选择性地启用测试。 测试模块在电缆上传输测试脉冲，测量反射幅度，计算电缆长度，并根据测量的幅度和计算的电缆长度确定电缆状态。 频率合成器与电缆通信，并且选择性地以第一端口上的多个频率输出多个信号。 插入损耗计算器接收第二端口上的信号并估计插入损耗。

公开(公告)号：US06982557B1

公开(公告)日：2006-01-03

申请号：US10979302

申请日：2004-11-02

Applicant: William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

Inventor： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

IPC: G01R31/02

CPC classification number: G01R31/083 ,  G01R31/088 ,  G01R31/11

Abstract: A physical layer device according to some implementations includes a cable tester that generates a test pulse on a cable and that determines a cable status including an open status, a short status, and a normal status. A cable impedance estimator communicates with the cable tester and estimates an impedance of the cable based on a reflection amplitude of the test pulse.

Abstract translation: 根据一些实现的物理层设备包括电缆测试器，其在电缆上产生测试脉冲，并且确定包括打开状态，短状态和正常状态的电缆状态。 电缆阻抗估计器与电缆测试器通信，并基于测试脉冲的反射幅度来估计电缆的阻抗。

公开(公告)号：US20050073675A1

公开(公告)日：2005-04-07

申请号：US10677587

申请日：2003-10-02

Applicant: William Lo

Inventor： William Lo

IPC: G01N21/88 ,  G01N21/95 ,  G01N21/956 ,  G01N21/00

CPC classification number: G01N21/9501 ,  G01N21/8806 ,  G01N21/956 ,  G01N2201/0853 ,  G01N2201/10 ,  G01N2201/101 ,  G01N2201/103

Abstract: A scanned optical system for use in optical probing applications provides a large Field of View (FOV) for objective lenses having high Numerical Aperture (NA), such as Solid Immersion Lenses (SIL's). This enables high resolution imaging of semiconductor devices for such applications as laser probing, TIVA/LIVA, OBIRCH, and photon emission timing analysis. A hybrid scanning optics configuration is disclosed to provide high resolution imaging over a small area along with low resolution imaging over a large area.

Abstract translation: 用于光学探测应用的扫描光学系统为具有高数值孔径（NA）的物镜（例如固体浸没透镜（SIL））提供了大视场（FOV）。 这样可实现用于激光探测，TIVA / LIVA，OBIRCH和光子发射时序分析等半导体器件的高分辨率成像。 公开了一种混合扫描光学配置，以在大面积上提供在小区域上的高分辨率成像以及低分辨率成像。

公开(公告)号：US06831479B2

公开(公告)日：2004-12-14

申请号：US10287527

申请日：2002-11-05

Applicant: William Lo

Inventor： William Lo

IPC: H03K19173

CPC classification number: H03K19/1732

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

Abstract translation: 通过减少生成配置数据所需的外部输入端子的数量，减少需要生成配置代码的诸如通信芯片或其他类型的芯片的半导体芯片的外部端子计数的电路。 电路包括多路复用器，每个复用器选择输出数据或配置数据，并且包括与芯片的相应外部输出端通信的输出。 选择器可连接在所选择的一个外部输出端子和与存储器通信的外部输入端子，以将输出端子上的配置数据串行输入到存储器以配置芯片。 因此，使用减少数量的外部输入端子为芯片生成配置码，从而减少芯片的整体外部终端计数。 电路和芯片可以体现在网络或以太网卡上。

公开(公告)号：US06741097B2

公开(公告)日：2004-05-25

申请号：US10287528

申请日：2002-11-05

Applicant: William Lo

Inventor： William Lo

IPC: H03K19173

CPC classification number: H03K19/1732

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

公开(公告)号：US6118809A

公开(公告)日：2000-09-12

申请号：US791587

申请日：1997-01-31

Applicant: William Lo

Inventor： William Lo

IPC: H04L25/24 ,  H04B3/36

CPC classification number: H04L25/242

Abstract: A repeater set provides for delaying a character of data that passes through the repeater set from one receive channel to a set of transmit channels. In providing for the delay of a character, the repeater set includes a delay calculator for calculating a character delay value. The repeater set then receives a character that is to be provided on a transmit channel and delays the character in a delay module for a period of time equal to the character delay value. The character delay value is determined by the delay calculator by first calculating a bit delay value and then converting the bit delay value into the character delay value.

Abstract translation: 中继器组提供用于将通过中继器组的数据的字符从一个接收信道延迟到一组发送信道。 在提供字符的延迟时，中继器组包括用于计算字符延迟值的延迟计算器。 然后，中继器组接收将在发送信道上提供的字符，并将延迟模块中的字符延迟等于字符延迟值的时间段。 字符延迟值由延迟计算器确定，首先计算位延迟值，然后将位延迟值转换为字符延迟值。

公开(公告)号：US5754525A

公开(公告)日：1998-05-19

申请号：US366808

申请日：1994-12-30

Applicant: William Lo ,  Ian Crayford

Inventor： William Lo ,  Ian Crayford

IPC: H04L12/22 ,  H04L12/44 ,  H04L29/06 ,  H04J3/26

CPC classification number: H04L12/44 ,  B60G17/0182 ,  H04L12/22 ,  H04L63/0236 ,  B60G2400/102 ,  B60G2400/202 ,  B60G2600/182 ,  B60G2600/1872 ,  B60G2600/1873 ,  B60G2800/162

Abstract: A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, delay disrupt response. A delay disrupt controller receives signals indicating retransmissions of fields from a data packet. These signals include a destination address field and a source address field. A plurality of memories, one associated with each port, determines the associated port's delay response to the data packet. Each memory stores a delay disrupt control code. When the delay disrupt control code for a particular port has a value indicating that the associated port is enabled to delay disruption of a data packet, security marking is disabled until the source address field is retransmitted from the particular port.

Abstract translation: 实现数据包掩蔽的安全中继器包括在每个端口基础上的可编程和选择性的延迟中断响应。 延迟中断控制器接收指示来自数据分组的字段重传的信号。 这些信号包括目的地址字段和源地址字段。 与每个端口相关联的多个存储器确定相关端口对数据分组的延迟响应。 每个存储器存储一个延迟中断控制码。 当延迟中断特定端口的控制代码具有指示相关端口被使能以延迟数据分组中断的值时，安全标记被禁用，直到源地址字段从特定端口重传为止。