Machine boot up protection structure for parallel power supply equipment
    91.
    发明申请
    Machine boot up protection structure for parallel power supply equipment 有权
    并联电源设备的机器启动保护结构

    公开(公告)号:US20070109702A1

    公开(公告)日:2007-05-17

    申请号:US11271831

    申请日:2005-11-14

    CPC classification number: H02H3/24 G06F1/305

    Abstract: A machine boot up protection structure for parallel power supply equipment provides a determination level to set the parallel power supply equipment in an ON condition. It has a control unit to receive a connection signal output by each of power supply units to compare with the determination level. If the comparison matches, all of the power supply units are activated to the ON condition. If the comparison does not match, all of the power supply units are set to an OFF condition. Thereby when the external power is not completely connected, some of the power supply units do not suffer from overloading and damaging.

    Abstract translation: 并联电源设备的机器启动保护结构提供了将并联电源设备设置为ON状态的确定级别。 它具有一个控制单元,用于接收由每个电源单元输出的连接信号以与确定电平进行比较。 如果比较匹配,所有电源单元都被激活到ON状态。 如果比较不匹配,所有电源单元都设置为OFF状态。 因此,当外部电源未完全连接时,一些电源单元不会受到过载和损坏的影响。

    Display device
    93.
    发明授权
    Display device 有权
    显示设备

    公开(公告)号:US09070334B2

    公开(公告)日:2015-06-30

    申请号:US12760539

    申请日:2010-04-14

    CPC classification number: G09G3/3648 G09G3/3607 G09G2300/0426

    Abstract: A display device includes a plurality of gate lines, data lines, first external gate tracking lines, and second external gate tracking lines. The first external gate tracking lines are substantially disposed in a border region of a substrate, and electrically connected with corresponding gate lines. The second external gate tracking lines are substantially disposed in the border region of the substrate, and electrically connected with corresponding gate lines. One of the first external gate tracking lines and a corresponding second external gate tracking line at least partially overlap with each other.

    Abstract translation: 显示装置包括多个栅极线,数据线,第一外部栅极跟踪线和第二外部栅极跟踪线。 第一外部栅极跟踪线基本上设置在基板的边界区域中,并与相应的栅极线电连接。 第二外部栅极跟踪线基本上设置在基板的边界区域中,并与相应的栅极线电连接。 第一外部栅极跟踪线之一和对应的第二外部栅极跟踪线至少部分地彼此重叠。

    Active device, pixel structure and display panel
    95.
    发明授权
    Active device, pixel structure and display panel 有权
    有源器件,像素结构和显示面板

    公开(公告)号:US08456582B2

    公开(公告)日:2013-06-04

    申请号:US13030133

    申请日:2011-02-18

    CPC classification number: G02F1/136213 G02F1/133707

    Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.

    Abstract translation: 提供有源器件,像素结构和显示面板。 像素结构包括扫描线,数据线,有源器件,栅极绝缘层,像素电极,电容器电极和电容器电介质层。 有源器件包括栅极,沟道,源极和漏极。 栅极电连接到扫描线。 源电连接到数据线。 栅极绝缘层设置在栅极和沟道之间。 像素电极电连接到漏极。 电容电极位于栅极绝缘层上。 电容器电介质层位于电容器电极和漏极之间。

    Display panel and active device array substrate thereof
    96.
    发明授权
    Display panel and active device array substrate thereof 有权
    显示面板及其有源器件阵列基板

    公开(公告)号:US08405646B2

    公开(公告)日:2013-03-26

    申请号:US12629884

    申请日:2009-12-03

    Abstract: A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.

    Abstract translation: 提供了包括有源器件阵列衬底,相对衬底和显示介质的显示面板。 有源器件阵列衬底包括衬底,扫描线,数据线,像素单元和数据信号传输线。 扫描线和数据线在衬底上限定多个像素区域。 每个像素单元分别设置在一个像素区域内,并且每个像素单元包括多个子像素单元。 相同像素单元内的子像素单元与相同的数据线电连接,并且相同像素单元内的每个子像素单元分别与扫描线之一电连接。 每个数据信号传输线与数据线之一电连接,并且数据信号传输线的延伸方向与扫描线的延伸方向基本平行。

    ACTIVE DEVICE ARRAY SUBSTRATE
    97.
    发明申请
    ACTIVE DEVICE ARRAY SUBSTRATE 有权
    主动设备阵列基板

    公开(公告)号:US20120112214A1

    公开(公告)日:2012-05-10

    申请号:US13353328

    申请日:2012-01-19

    CPC classification number: H01L27/1288 H01L27/1214

    Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.

    Abstract translation: 提供有源器件阵列衬底。 首先,提供具有显示区域和感测区域的基板。 然后,在基板的显示区域上设置第一图案化导体层。 栅极绝缘体设置在基板上。 图案化半导体层,第二图案化导体层和图案化感光介电层设置在栅极绝缘体上,其中第二图案化导体层包括源电极,漏电极和下电极,图案化的感光介电层覆盖第二 图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。 然后在衬底上设置钝化层。 之后,在钝化层上设置包括像素电极和上部电极的第三图案化导体层。

    Machine boot up protection structure for parallel power supply equipment
    98.
    发明授权
    Machine boot up protection structure for parallel power supply equipment 有权
    并联电源设备的机器启动保护结构

    公开(公告)号:US08032766B2

    公开(公告)日:2011-10-04

    申请号:US11271831

    申请日:2005-11-14

    CPC classification number: H02H3/24 G06F1/305

    Abstract: A machine boot up protection structure for parallel power supply equipment provides a determination level to set the parallel power supply equipment in an ON condition. It has a control unit to receive a connection signal output by each of power supply units to compare with the determination level. If the comparison matches, all of the power supply units are activated to the ON condition. If the comparison does not match, all of the power supply units are set to an OFF condition. Thereby when the external power is not completely connected, some of the power supply units do not suffer from overloading and damaging.

    Abstract translation: 并联电源设备的机器启动保护结构提供了将并联电源设备设置为ON状态的确定级别。 它具有一个控制单元,用于接收由每个电源单元输出的连接信号以与确定电平进行比较。 如果比较匹配,所有电源单元都被激活到ON状态。 如果比较不匹配,所有电源单元都设置为OFF状态。 因此,当外部电源未完全连接时,一些电源单元不会受到过载和损坏的影响。

    PIXEL ARRAY
    99.
    发明申请
    PIXEL ARRAY 有权
    像素阵列

    公开(公告)号:US20110233567A1

    公开(公告)日:2011-09-29

    申请号:US12788301

    申请日:2010-05-27

    CPC classification number: H01L27/12 G02F1/136286 G02F2201/40 H01L27/124

    Abstract: A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.

    Abstract translation: 像素阵列位于衬底上并且包括多个像素组。 每个像素组包括第一扫描线,第二扫描线,数据线,数据信号传输线,第一像素单元和第二像素单元。 数据线不平行于第一和第二扫描线。 数据信号传输线平行于第一和第二扫描线设置并与数据线电连接。 第一和第二扫描线之间的距离小于数据信号传输线与第一和第二扫描线之一之间的距离。 第一像素单元电连接到第一扫描线和数据线。 第二像素单元电连接到第二扫描线和数据线。

    PIXEL STRUCTURE AND METHOD FOR FABRICATING THE SAME
    100.
    发明申请
    PIXEL STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
    像素结构及其制作方法

    公开(公告)号:US20110165742A1

    公开(公告)日:2011-07-07

    申请号:US13052114

    申请日:2011-03-21

    Applicant: Yu-Cheng Chen

    Inventor: Yu-Cheng Chen

    CPC classification number: H01L27/1288 H01L27/1214

    Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

    Abstract translation: 一种制造像素结构的方法包括提供具有像素区域的衬底。 在衬底上形成第一金属层,栅极绝缘体和半导体层,并通过使用第一半色调掩模或灰色蒙版掩模进行图案化以形成晶体管图案,较低的电容图案和较低的电路图案。 接下来,依次形成覆盖三个图案的电介质层和电极层,并对其进行图案化以暴露下部电路图案的一部分,下部电容图案的一部分和晶体管图案的源极/漏极区域。 通过使用第二半色调掩模或灰度蒙版来形成在电极层和电极层上形成的第二金属层,以形成上部电路图案,源极/漏极图案和上部电容图案。 电极层的一部分构成像素电极。

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