公开(公告)号：US20080258245A1

公开(公告)日：2008-10-23

申请号：US12147327

申请日：2008-06-26

申请人： Leonard Forbes ,  Kie Y. Ahn ,  Luan C. Tran

发明人： Leonard Forbes ,  Kie Y. Ahn ,  Luan C. Tran

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/40114 ,  H01L29/4941 ,  H01L29/6656

摘要： One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

摘要翻译： 本发明的一个方面包括形成半导体结构的方法。 形成图案线以包括第一层和第二层。 第一层包括硅，第二层包括金属。 线具有包括第一层限定部分和第二层限定部分的至少一个侧壁边缘。 沿着至少一个侧壁边缘形成第三层。 第三层包括硅并沿着侧壁边缘的第一层定义部分和侧壁边缘的第二层限定部分。 第三层的硅与第二层的金属反应，沿着侧壁边缘的第二层限定部分形成硅化物。 去除第三层的硅以留下第一层的硅，第二层的金属和硅化物。

公开(公告)号：US20080227293A1

公开(公告)日：2008-09-18

申请号：US12119831

申请日：2008-05-13

申请人： Luan C. Tran ,  John Lee ,  Zengtao "Tony" Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan C. Tran ,  John Lee ,  Zengtao "Tony" Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/768 ,  H01L21/306

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

摘要翻译： 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US20080162781A1

公开(公告)日：2008-07-03

申请号：US11618658

申请日：2006-12-29

申请人： Gordon Haller ,  Luan C. Tran

发明人： Gordon Haller ,  Luan C. Tran

IPC分类号： G11C5/02 ,  G06F12/00 ,  H01L21/8239

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531

摘要： Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top surface of the plurality of layer, the first plurality of pitch-multiplied spacers being above the central region of the substrate, and a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary.

摘要翻译： 本发明的实施例提供了包括包括中心区域和外围区域的基板的装置，方法和系统; 在所述基板的表面上方的多个层，在所述多个层的顶表面上的第一多个间距倍数间隔件，所述第一多个间距倍数间隔件在所述基板的中心区域的上方，以及第二多个 在所述多个层的顶表面上的间距倍增间隔物，所述第二多个间距倍增间隔物在所述外围区域上方，并且包括至少一个间距倍增间隔物，所述间距倍增间隔物具有距所述至少一个间距倍数间隔物 在边界有一个表面。

公开(公告)号：US07384847B2

公开(公告)日：2008-06-10

申请号：US11111625

申请日：2005-04-21

申请人： Luan C. Tran ,  Fred D. Fishburn

发明人： Luan C. Tran ,  Fred D. Fishburn

IPC分类号： H01L21/336

CPC分类号： H01L27/10888 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/24 ,  Y10S257/906 ,  Y10S257/908

摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.

摘要翻译： 本发明包括可用于形成存储器阵列的存储器阵列和方法。 在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。 可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。 可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。 在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。 然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

公开(公告)号：US07341901B2

公开(公告)日：2008-03-11

申请号：US09848846

申请日：2001-05-03

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/00

CPC分类号： H01L21/823412 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/10894

摘要： Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

摘要翻译： 描述形成集成电路的半导体处理方法。 在一个实施例中，在衬底上形成存储器电路和外围电路。 外围电路包括第一和第二类型的MOS晶体管。 在比第一类型的所有外围MOS晶体管少的情况下，将第二类型的晕轮植入物导入第一类型的MOS晶体管。 在另一个实施例中，多个n型晶体管器件形成在衬底上并且包括存储器阵列电路和外围电路。 至少一些单独的外围电路n型晶体管器件被部分屏蔽，并且对部分屏蔽的外围电路n型晶体管器件的未屏蔽部分进行晕圈注入。 在另一个实施例中，源极和漏极区域中的仅一个区域的至少一部分被掩蔽，并且源极和漏极区域中的另一个的至少一部分被暴露用于至少一些外围电路n型晶体管器件 。 相对于源极和漏极区域的暴露部分进行晕轮植入。 在另一个实施例中，使用公共屏蔽步骤，并且在衬底上形成的器件进行晕轮注入，该器件包括存储器电路和外围电路，其足以赋予器件中的至少三个器件三个不同的相应阈值电压。

公开(公告)号：US07294903B2

公开(公告)日：2007-11-13

申请号：US11216915

申请日：2005-08-31

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/00

CPC分类号： H01L21/823481 ,  H01L27/10894 ,  H01L27/10897

摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

摘要翻译： 描述形成晶体管的半导体处理方法，形成动态随机存取存储器电路的半导体处理方法以及相关的集成电路。 在一个实施例中，有源区域形成在衬底上，其中一个有源区域具有小于1微米的宽度，并且一些有源区域具有不同的宽度。 在有源区上形成栅极线以提供具有不同阈值电压的晶体管。 优选地，晶体管被提供有不同的阈值电压，而不用于晶体管的单独沟道注入。 在另一个实施例中，在衬底内形成多个浅沟槽隔离区，并且限定多个有效区域，其宽度至少有一个不大于约一微米（或更小），其中一些宽度优选地不同 。 一个或多个栅极线可以耦合到相应的有源区以提供单独的晶体管，晶体管对应于具有不同阈值电压的不同宽度的有源区。 在另一个实施例中，制造具有不同阈值电压的两个场效应晶体管，而不使用用于晶体管之一的单独沟道注入。

公开(公告)号：US07227227B2

公开(公告)日：2007-06-05

申请号：US11211374

申请日：2005-08-24

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L29/76

CPC分类号： H01L27/10894 ,  H01L21/28044 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/1041 ,  H01L29/4916 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78 ,  Y10S438/919 ,  Y10S438/975

摘要： The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along-gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

摘要翻译： 本发明包括具有一对沟道区的半导体结构，所述沟道区具有被铟掺杂并被硼包围的子区。 一对晶体管结构位于沟道区上方并由隔离区隔开。 晶体管具有比下面的子区域更宽的栅极。 本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。 每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。 源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下延伸更远的源极/漏极区域。 本发明还包括形成半导体结构的方法。

公开(公告)号：US07176093B2

公开(公告)日：2007-02-13

申请号：US10376106

申请日：2003-02-26

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/10894

摘要： Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

摘要翻译： 描述形成集成电路的半导体处理方法。 在一个实施例中，在衬底上形成存储器电路和外围电路。 外围电路包括第一和第二类型的MOS晶体管。 在比第一类型的所有外围MOS晶体管少的情况下，将第二类型的晕轮植入物导入第一类型的MOS晶体管。 在另一个实施例中，多个n型晶体管器件形成在衬底上并且包括存储器阵列电路和外围电路。 至少一些单独的外围电路n型晶体管器件被部分屏蔽，并且对部分屏蔽的外围电路n型晶体管器件的未屏蔽部分进行晕圈注入。 在另一个实施例中，源极和漏极区域中的仅一个区域的至少一部分被掩蔽，并且源极和漏极区域中的另一个的至少一部分被暴露用于至少一些外围电路n型晶体管器件 。 相对于源极和漏极区域的暴露部分进行晕轮植入。 在另一个实施例中，使用公共屏蔽步骤，并且在衬底上形成的器件进行晕轮注入，该器件包括存储器电路和外围电路，其足以赋予器件中的至少三个器件三个不同的相应阈值电压。

公开(公告)号：US07170124B2

公开(公告)日：2007-01-30

申请号：US10968429

申请日：2004-10-19

申请人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

发明人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10888

摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

公开(公告)号：US07157775B2

公开(公告)日：2007-01-02

申请号：US10367520

申请日：2003-02-13

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L29/76

CPC分类号： H01L27/10894 ,  H01L21/28044 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/1041 ,  H01L29/4916 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78 ,  Y10S438/919 ,  Y10S438/975

摘要： The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying subregions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

摘要翻译： 本发明包括具有一对沟道区的半导体结构，所述沟道区具有被铟掺杂并被硼包围的子区。 一对晶体管结构位于沟道区上方并由隔离区隔开。 晶体管具有比底层子区域宽的栅极。 本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。 每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。 源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下延伸更远的源极/漏极区域。 本发明还包括形成半导体结构的方法。